N. J. Gaspard

Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The experimental results agree very well with simulation predictions and confirm that event error rates can be reduced dramatically using effective layout design.

Effect of Transistor Density and Charge Sharing on Single-Event Transients in 90-nm Bulk CMOS

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width.

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

In this paper, the alpha-particle induced soft error rate of two flip-flops are investigated as a function of operating frequency between 80 MHz and 1.2 GHz. The two flip-flops-an unhardened D flip-flop and a hardened pseudo-DICE flip-flop were designed in a TSMC 40 nm bulk CMOS technology. The error rates of both flip-flops increase with frequency. Analyses show that an internal single-event transient based upset mechanism is responsible for the frequency dependence of the error rates.

Electron-Induced Single-Event Upsets in Static Random Access Memory

We present experimental evidence of single-event upsets in 28 and 45 nm CMOS SRAMs produced by single energetic electrons. Upsets are observed within 10% of nominal supply voltage for devices built in the 28 nm technology node. Simulation results provide supporting evidence that upsets are produced by energetic electrons generated by incident X-rays. The observed errors are shown not to be the result of “weak bits” or photocurrents resulting from the collective energy deposition from X-rays. Experimental results are consistent with the bias sensitivity of critical charge for direct ionization effects caused by low-energy protons and muons in these technologies. Monte Carlo simulations show that the contributions of electron-induced SEU to error rates in the GEO environment depend exponentially on critical charge.

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends. The results show that as technologies scale, D flip-flop single-event upset cross sections decrease while redundant storage node flip-flops cross sections may stay the same or increase depending on the layout spacing of storage nodes. As technology feature sizes become smaller, D flip-flop single-event upset cross sections approach redundant storage node hardened flip-flops cross sections for particles with high linear energy transfer values. Experimental results show that redundant storage node designs provide > 100X improvement in single-event upset cross section over DFF for ion linear energy transfer values below 10 MeV-cm2/mg down to 28-nm feature sizes.

Impact of Well Structure on Single-Event Well Potential Modulation in Bulk CMOS

Perturbations in N-well potential have been shown to strongly affect the charge collection, charge sharing, and parasitic bipolar transistor characteristics. In this paper, temporal and spatial characteristics of the well-potential modulation are characterized through 3-D TCAD simulations. Effects of well-contact layout, ion energy, and technology process parameters for a 90-nm bulk CMOS process are investigated.

Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

Alpha particle irradiations of 28-nm combinational logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the combinational logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from combinational logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A built-in-self-test circuit for the measurement of single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows for the extraction of measurement-induced uncertainty. SET pulse width data from heavy-ion experiments are provided and compared to technology computer aided design simulations. A method for compensating for the measurement bias and skew is provided.

The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

Impact of technology scaling on the combinational logic soft error rate

Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling. This rate of decrease for the logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of combinational logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which combinational logic SER exceeds latch SER decreases with scaling. Factors that influence logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.