T. Saraya

Coulomb blockade oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabricated by anisotropic etching on a silicon-on-insulator substrate

We have developed a very controllable fabrication process of an extremely narrow (∼10 nm) quantum wire metal‐oxide‐semiconductor field‐effect transistor (MOSFET) on a separation‐by‐implanted‐oxygen (SIMOX) substrate using anisotropic etching and selective oxidation technique. The drain current versus gate voltage characteristics show oscillations caused by Coulomb blockade even at room temperature. The oscillations split into several sharp peaks when the temperature is decreased, indicating that the channel is separated by several serial coupled quantum dots and that the quantum levels of these dots correspond to the observed fine peaks.

Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG

The static noise margin (SNM) as well as V<inf>th</inf>, g<inf>m</inf>, body factor, and drain-induced-barrier-lowering (DIBL) in individual transistors in SRAM cells are directly measured by 16k bit device-matrix-array (DMA) SRAM TEG. It is found that, besides V<inf>th</inf> variability, DIBL variability degrades SRAM stability and its V<inf>dd</inf> dependence while the variability of g<inf>m</inf> and body factor has only a small effect.

Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method

In this paper, we report our experimental study on electron mobility in silicon gate-all-around (GAA) nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100)-oriented silicon-on-insulator (SOI) substrates. With the aim of accurate mobility measurement, the improved split capacitance–voltage (C–V) method is utilized to remove parasitic resistance and capacitance. Accurate electron mobility in [100]-directed nanowires is achieved for the first time and shows high electron mobility that approaches the (100) bulk universal curve, while electron mobility in [110]-directed nanowires shows large degradation from the universal curve. The underlying physical mechanisms of mobility behaviors in nanowires on (100)-oriented SOI substrates are also investigated.

Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG

A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM follows the normal distribution up to ±4σ. It is also found that the cell stability is worse than circuit simulation using Vth of measured 6 transistors. Furthermore, the post-fabrication self-convergence scheme by NBTI stress is applied to DMA SRAM TEG and the cell stability improvement is demonstrated experimentally for the first time.

Experimental Investigations of Electron Mobility in Silicon Nanowire nMOSFETs on (110) Silicon-on-Insulator

Investigations on electron mobility characteristics in gate-all-around silicon nanowire nMOSFETs on (110)-oriented silicon-on-insulator substrates have been described on the basis of the advanced split capacitance-voltage (C- V) method. It is found that the electron mobility in [110]-directed nanowires approaches and is even higher than that in [100]-directed nanowires as the nanowire width is reduced. As a result, mobility degradation in (110) planar nMOSFETs can be recovered to some extent by utilizing [110]-directed nanowires on (110)-oriented substrates. The underlying physical mechanisms are also discussed.

Characterization of precisely width-controlled Si quantum wires fabricated on SOI substrates

Abstract Silicon quantum wire structures with precisely controlled widths have been successfully fabricated on an SOI substrate by an anisotropic etching technique. The width of the wires does not depend on the lithography limit but solely on the thickness of the Si film of the SOI substrate. It is demonstrated that the wires are straight even if the lithography patterns are fluctuated. The minimum width is estimated to be less than 10 nm. This technique has been applied to fabricating a quantum wire FET, which shows fine peaks in drain current as a function of the gate voltage at low temperatures due to the Coulomb blockade of the single electron tunneling. The oscillations remain even at room temperature.

Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding

We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of Au/SiO2 at a low temperature of 200°C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.

Floating body effects in 0.15 /spl mu/m partially depleted SOI MOSFETs below 1 V

Summary form only. The SOI MOSFET has attracted much attention as a very low power, low voltage device. The supply voltage is reduced to less than 1 V for extreme low power applications. The floating body effects, which is one of the most serious problems in partially depleted (PD) SOI MOSFETs, would be very different when the supply voltage is reduced below 1 V, because the bipolar effect and the impact ionization would be suppressed. However, most of the previous studies on the floating body effects have been reported in the regime of 1.5-3 V. In this paper, we have investigated the floating body effects in 0.15 /spl mu/m PD MOSFETs below 1 V.

Ultra-low power and ultra-low voltage devices and circuits for IoT applications

This paper reports new device trends of ultra-low power, ultra-low leakage, and ultra-low voltage for IoT applications. The SOTB technology achieves subthreshold leakage as low as 0.2pA/μm. Some device/circuit tricks for non-volatility and ultra-low voltage operation are reviewed.

Ratchet effect study in Si/SiGe heterostructures in the presence of asymmetrical antidots for different polarizations of microwaves

Abstract In this work, we studied the photovoltage response of an antidot lattice to microwave radiation for different antidot parameters. The study was carried out in a Si/SiGe heterostructure by illuminating the antidot lattice with linearly polarized microwaves and recording the polarity of induced photovoltage for different angles of incidence. Our study revealed that with increased antidot density and etching depth, the polarity of induced photovoltage changed when the angle of incidence was rotated 90 degrees. In samples with large antidot density and/or a deeply etched antidot lattice, scattering was dominated by electron interaction with the asymmetrical potential created by semicircular antidots. The strong electron–electron interaction prevailed in other cases. Our study provides insight into the mechanism of interaction between microwaves and electrons in an antidot lattice, which is the key for developing an innovative ratchet-based device. Moreover, we present an original and fundamental example of antidot lattice etching through the use of a two-dimensional electron gas. This system deals with a hole lattice instead of an electron depletion in the antidot lattice region.