Ken Shimizu

Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group of 16-kb SRAM cells, and the correlation between the SRAM noise margin and the cell transistor variability is analyzed. It is found that each cell shows a very different supply voltage Vdd dependence of the static noise margin (SNM), and this scattered Vdd dependence of the SNM is not explained by the measured threshold voltage Vth variability alone, indicating that the circuit simulation taking only the Vth variability into account will not predict the SRAM stability precisely at low supply voltage.

Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI

Experimental investigations of silicon nanowire mobility characteristics on (100) SOI as shrinking nanowire width to sub-10 nm are reported. Accurate mobility estimations by advanced split CV method for 50~1000 nanowires are performed. For the first time, electron and hole mobility in [100]-directed nanowires are studied and compared with [110] nanowires. It is shown that both electron and hole mobility decreases monotonically and electron mobility of [100]-directed nanowire tends to be comparable to that of [110]-directed nanowire as decreasing nanowire width.

Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme

The bias scheme of the variable body-factor fully depleted (FD) silicon-on-insulator (SOI) MOSFET, which has been previously proposed, is reexamined. Using a new scheme, the inversion and accumulation on the substrate in the active state can be avoided, and thus, ac performance in the active state is not degraded even with extremely thin buried-oxide (BOX), owing to the depletion of the substrate. Moreover, subthreshold leakage can be sufficiently suppressed in the standby state, owing to extremely thin BOX. This scheme provides threshold-voltage adjustability for the suppression of interdie and within-die variation in the active state. This device scheme is also applicable to multichannel FD SOI MOSFETs including FinFETs with a low-aspect-ratio fin, where the back-bias scheme can be applied

Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method

In this paper, we report our experimental study on electron mobility in silicon gate-all-around (GAA) nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100)-oriented silicon-on-insulator (SOI) substrates. With the aim of accurate mobility measurement, the improved split capacitance–voltage (C–V) method is utilized to remove parasitic resistance and capacitance. Accurate electron mobility in [100]-directed nanowires is achieved for the first time and shows high electron mobility that approaches the (100) bulk universal curve, while electron mobility in [110]-directed nanowires shows large degradation from the universal curve. The underlying physical mechanisms of mobility behaviors in nanowires on (100)-oriented SOI substrates are also investigated.

Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG

A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM follows the normal distribution up to ±4σ. It is also found that the cell stability is worse than circuit simulation using Vth of measured 6 transistors. Furthermore, the post-fabrication self-convergence scheme by NBTI stress is applied to DMA SRAM TEG and the cell stability improvement is demonstrated experimentally for the first time.

Threshold Voltage Dependence of Threshold Voltage Variability in Intrinsic Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with Ultrathin Buried Oxide

Threshold voltage (Vth) variability due to random dopant fluctuations in intrinsic channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with an ultrathin buried oxide is investigated by three-dimensional device simulation. It is found that, in contrast to bulk and doped channel SOI MOSFETs, Vth variations in intrinsic channel SOI MOSFETs decrease with increasing Vth. A device design guideline for intrinsic channel SOI MOSFETs is also discussed.

Origin of “current-onset voltage” variability in scaled MOSFETs

Present work analyzes the cause of “current-onset voltage” variability, which has been newly found to largely affect drain current variability [1]. It is found by 3D device simulation that the “current-onset voltage” variability is determined by how largely the channel potential fluctuates by random dopant disposition. Reducing RDF will suppress both threshold voltage and current-onset voltage variability as well.

Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultrathin Body nMOSFETs

Electron mobility in ultrathin body MOSFETs in double-gate (DG) operation has been investigated with SOI thickness of less than 4 nm for the first time. Although mobility degradation in DG compared to single gate occurs with SOI thickness of larger than 2 nm, the degradation is suppressed with SOI thickness of 1.7 nm. This suppression mechanism is explained by strong quantum confinement effect by an extremely thin SOI layer.

Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin Body Single- and Double-Gate MOSFETs with SOI Thickness of Less Than 4 nm

Mobility in single-gate (SG) and double-gate (DG) ultra-thin body (UTB) SOI MOSFETs under uniaxial tensile stress has been systematically examined. Mobility enhancement in both UTB nMOSFETs and pMOSFETs by stress is experimentally demonstrated for the first time. The enhancement in UTB nMOSFETs is larger than the prediction by theory. The mobility enhancement by stress in DG UTB nMOSFETs and pMOSFETs is also observed. The enhancement may originate from not only the subband energy shift but effective mass change.

Experimental Study on Mobility Universality in (100) Ultrathin Body nMOSFETs with SOI Thickness of 5 nm

In this paper, we describe the experimental determination of the η of mobility universality in ultrathin body (UTB) n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs) with silicon-on-insulator (SOI) thickness ranging from 30 down to 5 nm. It is found experimentally for the first time that η is larger than 1/2 when SOI thickness is smaller than 12 nm. The meaning of η is discussed in terms of the occupancy of the lowest subband of the 2-fold valley.