Tadahiro Ohmi

Growth of native oxide on a silicon surface

The control factors controlling the growth of native silicon oxide on silicon (Si) surfaces have been identified. The coexistence of oxygen and water or moisture is required for growth of native oxide both in air and in ultrapure water at room temperature. Layer‐by‐layer growth of native oxide films occurs on Si surfaces exposed to air. Growth of native oxides on n‐Si in ultrapure water is described by a parabolic law, while the native oxide film thickness on n+‐Si in ultrapure water saturates at 10 A. The native oxide growth on n‐Si in ultrapure water is continuously accompanied by a dissolution of Si into the water and degrades the atomic flatness at the oxide‐Si interface, producing a rough oxide surface. A dissolution of Si into the water has not been observed for the Si wafer having surface covered by the native oxide grown in air. Native oxides grown in air and in ultrapure de‐ionized water have been demonstrated experimentally to exhibit remarkable differences such as contact angles of ultrapure wa...

Dependence of thin-oxide films quality on surface microroughness

The effects of silicon surface microroughness on electrical properties of thin-oxide films, such as breakdown electric field intensity (E/sub BD/) and time-dependent dielectric breakdown (Q/sub BD/), have been studied, where the microroughnesses of silicon and silicon dioxide surfaces are evaluated by the scanning tunneling microscope (STM) and the atomic force microscope (AFM), respectively. An increase of surface microroughness has been confirmed to severely degrade the E/sub BD/ and Q/sub BD/ characteristics of thin-oxide films with thicknesses of 8-10 nm and to simultaneously decrease channel electron mobility. An increase of surface microroughness has been demonstrated to originate mainly from wet chemical cleaning processing based on the RCA cleaning concept, particularly the ammonium-hydrogen-peroxide cleaning step. In order to keep the surface microroughness at an initial level, the content ratio of NH/sub 4/OH/H/sub 2/O/sub 2//H/sub 2/O solution has been set at 0.05:1:5 and the room-temperature DI water rinsing has been introduced right after the NH/sub 4/OH/H/sub 2/O/sub 2//H/sub 2/O cleaning step in conventional RCA cleaning procedure. >

Control factor of native oxide growth on silicon in air or in ultrapure water

Native silicon (Si) oxide growth on Si (100) wafers in air and in ultrapure water at room temperature requires coexistence of water and oxygen in the air and ultrapure water ambients. The growth rate data on n‐, n+‐, and p+‐Si (100) in air indicate layer‐by‐layer growth of an oxide. The growth rate on n‐Si (100) in ultrapure water may be governed by a parabolic law. For native oxide growth in ultrapure water, the number of Si atoms dissolved in ultrapure water is over one order of magnitude larger than the number of Si atoms contained in the grown native oxide film. The structural difference between the native oxide film in air and in ultrapure water is also discussed.

Total Room Temperature Wet Cleaning for Si Substrate Surface

An ultraclean wafer surface is crucial for high quality processing in Si technologies. Cleaning of the Si wafer surface has been accomplished by RCA wet cleaning for the past quarter century, where there exists high temperature processes consisting of H 2 SO 4 /H 2 O 2 /H 2 O, NH 4 OH/H 2 O 2 /H 2 O, and HCl/H 2 O 2 /H 2 O treatment. Thus, RCA cleaning requires a large number of processing steps, resulting in the consumption of a huge volume of liquid chemicals and ultrapure water, and simultaneously consuming a large volume of clean air exhaust to suppress chemical vapor from getting into the clean room. Total room temperature wet cleaning consisting of five cleaning steps has been developed or Si wafer surfaces, where consumption volume of liquid chemicals and ultrapure water has been reduced less than 1% and 5%, respectively, compared to that of RCA cleaning. The newly developed cleaning technology has been confirmed to contribute to future simplified and low cost manufacturing of ultralarge scale integrated devices.

Mechanism of Metallic Particle Growth and Metal‐Induced Pitting on Si Wafer Surface in Wet Chemical Processing

To understand the mechanism of noble‐metal adhesion in wet processes, the behavior of Cu adhesion to the Si surface in various chemical solutions, the shape and chemical composition of Cu contaminants adhering to Si surfaces, the surface microroughness of Si surfaces, and the influence of the type of the substrates are investigated. The results show that Cu ion deposits on the Si surface in the form of metallic particles in wet chemical processing, that Cu deposition in solutions causes pits to be formed on the Si surface, and that, on a patterned substrate, Cu deposits on the Si surface but not on the surface. The experimental results imply a Cu deposition mechanism. In a dilute solution, the Si surface beneath the Cu particles is etched away to become and a pit is made. Contamination with noble metals is critical. The mechanism for metal deposition may apply to noble metals in general. These metallic impurities must not be introduced into any wet chemical solution or ultrapure water when a bare Si surface is exposed.

Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation

Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness

The effect of the Si-SiO/sub 2/ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH/sub 4/OH in the NH/sub 4/OH-H/sub 2/O/sub 2/-H/sub 2/O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO/sub 2/ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm/sup 2//V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5*10/sup 17/ cm/sup -3/, i.e. the electron bulk mobility is 400 cm/sup 2//V-s. It goes down to 100 cm/sup 2//V-s when the interface microroughness exceeds 1 nm.<<ETX>>

Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications

For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of binary-logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The nu MOS logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented. >

Low‐temperature silicon selective deposition and epitaxy on silicon using the thermal decomposition of silane under ultraclean environment

An ultraclean hot‐wall low‐pressure chemical vapor deposition (CVD) system was developed and Si films were deposited on single‐crystal Si and SiO2 using ultraclean SiH4 and H2 gases in the temperature range 600–850 °C under an ultraclean environment. As a result of ultraclean processing, an incubation period of Si deposition only on SiO2 was found, and low‐temperature Si selective deposition and epitaxy on Si were achieved without addition of HCl under deposition conditions where only nonselective polycrystalline Si growth could be obtained in conventional CVD systems.

New era of silicon technologies due to radical reaction based semiconductor manufacturing

Current semiconductor technology, the so-called the molecule reaction based semiconductor manufacturing, now faces a very severe standstill due to the drastic increase of gate leakage currents and drain leakage currents. Radical reaction based semiconductor manufacturing has been developed to completely overcome the current standstill by introducing microwave excited high density plasma with very low electron temperatures and without accompanying charge-up damage.The introduction of radical reaction based semiconductor manufacturing has made it possible to fabricate LSI devices on any crystal orientation Si substrate surface as well as (100) Si substrate surfaces, and to eliminate a very severe limitation to the antenna ratio in the circuit layout patterns, which is strictly limited to less than 100–200 in order to obtain a relatively high production yield.