Takae Sukegawa

A new leakage mechanism of Co salicide and optimized process conditions [for CMOS]

We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-/spl mu/m CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo simulation. We identified abnormal CoSi/sub x/ spikes under the Co silicide film, as being the origin of the localized leakage current. These CoSi/sub x/ spikes grow rapidly only during annealing between 400 and 450/spl deg/C for 30 s when Co/sub 2/Si phase is formed. These spikes never grow during annealing at over 500/spl deg/C, and decrease with high temperature annealing. A minimum leakage current results by optimized annealing at between 800 and 850/spl deg/C for 30 s. This is because a trade-off exists between reducing the CoSi/sub x/ spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900/spl deg/C.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

First Quantitative Observation of Local Temperature Fluctuation in Millisecond Annealing

We report, for the first time, a detailed study of the 100 mum-scaled emissivity and temperature variation in millisecond annealing (MSA) depending on the Si trench structure, the shallow trench isolation (STI) structure, and transistor structure measured by Thermawave method. Flash lamp annealing (FLA) was applied as MSA technique. In case of Si trench structure with varying the trench depth, the relation between the trench depth and emissivity was clarified quantitatively. It was found that micro temperature variation within a chip driven by the emissivity variation exceeds of 100degC as the transistor structure was annealed by FLA.

Transmission Electron Microscopy Observation of CoSix Spikes in Si Substrates during Co-silicidation Process

Needle-like spikes penetrating into Si substrates have been detected by cross-sectional transmission electron microscopy (TEM) studies of Co silicide/Si interfaces. The spikes are crystalline CoSix and form at annealing temperatures of 400–425° C, when the transformations of Co→Co2Si and Co2Si→CoSi are both taking place. They sometimes extend to the p/n junction depth of 100 nm. During annealing at above 500° C, they become spherical and their density decreases. The temperature range in which CoSix spikes are formed and extend to near the junction depth corresponds well with that for the onset of junction leakage. Therefore, this supports the conclusion that Co silicide junction leakage is caused by such spike formation.

Leakage mechanism and optimized conditioms of Co salicide process for deep-submicron CMOS devices

For high performance deep-submicron CMOS devices, the TiN capped Co salicide process is one of the most attractive candidate to reduce the sheet resistances of the narrow gate, source, and drain regions. However, the increased leakage current for a very shallow p-n junction is a serious problem. We clarified a new leakage mechanism of the Co salicided junction. Measurements and simulated results of the leakage current revealed that the leakage current flows from many localized points. These leakage points were caused by CoSi spikes growing from the silicide film, which we observed by TEM analysis. We then optimized the Co salicide process conditions to reduce the leakage current in the ultra-shallow junctions of deep-submicron CMOS devices.

Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology

We developed a novel junction profile engineering technique that uses laser spike annealing (LSA): LSA is implemented prior to spike-RTA to modulate the junction profile. With this technique, we can improve the performance of MOSFETs more effectively than conventional techniques. In addition, it enables us to use lower LSA temperatures with wide process window (at least 60degC) because of its low sensitivity to LSA temperatures within a certain range, while the conventional ways require ultra high temperatures to improve the device performance. We applied this technique to 45-nm node high performance (HP) CMOS devices with a gate length of 32-nm. A reduction in the source-drain parasitic resistance achieves 8.8% / 5% of improvements in the saturation on-current (Ion) for PMOS / NMOS, and Ion = 750(P) / 1030(N) [muA/mum] for Ioff = 100 [nA/mum] at Vdd= 1.0V. We also demonstrated the advantages of this technique by evaluating the performance of ring oscillators, SRAM yields and accuracy of precision poly resistors from the LSI manufacturing point of view.

Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

We have developed a novel junction profile engineering using laser spike annealing (LSA) with co-implant and applied it to sub-30-nm strained CMOS devices. A 55% reduction in source-drain extension (SDE) resistance achieves a 15% improvement in the saturation on-current (I _on) at a 28-nm gate length for PMOS. A reduction in the source-dram parasitic resistance enables an over 50% improvement in the linear on-current (I_dlin) by capping layer stress on the 29-nm gate length, which is about a 10% increase in the I_dlin improvement ratio compared to that of the control device, and a 28% of I _on enhancement gave us I_on= 460 muA/mum for I _off= 100 nA/mum at V_d= -1.0 V. For NMOS, low resistance SDE can be obtained without inducing the deterioration of the V_th-rolloff thanks to the halo profile modulation, and 6% of I_on enhancement was achieved at a 29-nm gate length, and I _on= 925 muA/mum for I_off= 100 nA/mum at V _d= 1.0 V was obtained

A comparative study of leakage mechanism of Co and Ni salicide processes

We investigated the leakage mechanisms of both Co and Ni salicide processes. Statistical analyses of the junction leakage and a direct light observation of the leakage points from Co and Ni salicided junctions revealed that Ni salicide also shows many localized spots that cause leakage just like those in the Co salicide case, but in the Ni salicide case, the spots are along the LOCOS edge. Leakage currents were successfully simulated by means of a new spike-leakage model that considers both area and peripheral dependent spike leakage. To explain the subsequent results, we proposed a stress induced spike growth model. Working from this model, we developed a spike-leakage-free Co salicide process using a Ge pre-amorphization step.

Total temperature fluctuation of a patternned wafer in the millisecond annealing

This paper describes the total temperature fluctuation within patterned wafers based on sub-100μm-scaled microscopic temperature non-uniformity within a chip, and mm-scaled macroscopic temperature variation within blanket wafers in laser spike annealing (LSA) and Flash Lamp Annealing (FLA). Temperature distribution within a chip and non-uniformity within blanket wafers are obtained by thermal wave (TW) method and conventional 4 point probe sheet resistance measurement, respectively. In the case of LSA, it was found that the local temperature is less dependent on pattern density. However, hot spots which local temperature is 50 °C higher than the surrounding area occur near large active areas. In the case of FLA, the local temperature depends strongly on pattern pitch. We did not find the hot spot. Total temperature fluctuations of pattern wafers of LSA and FLA reach about 90 and 120 °C.

Drive Current Enhancement in Sub- 40-nm CMOS Devices by Higher Carrier Activation with Laser Spike Annealing

We thoroughly investigated the impact of higher carrier activation using laser spike annealing (LSA). In our experiments, the annealing time was set at 200 μs and the peak annealing temperature was estimated at 1350°C, which was 350°C higher than that of the spike-rapid thermal annealing (RTA) used in this study. We analyzed the source-drain parasitic resistance and the gate depletion suppression to demonstrate that LSA can improve I on currents while suppressing the short channel effect in sub-40-nm complementary metal oxide semiconductor devices, compared to the conventional spike-RTA. The gate depletion was suppressed by 0.18 and 0.15 nm for p-MOS and n-MOS devices, respectively, and, channel conductance can actually be improved with it. Using LSA, a shallower junction depth and shorter source-drain extension (SDE) overlap length was achieved for the same SDE sheet resistance. As a result, the V th roll-off improved dramatically. Moreover, the higher carrier activation produced improvements in the /on current of 3%/14% for p-MOS/n-MOS transistors. We also demonstrate that a 13% improvement in I on was achieved for p-MOS at the same V th -roll-off as the spike-RTA device, due to the simultaneous suppression of gate depletion and the reduction in the source-drain parasitic resistance.