K. Okano

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different beta-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm fin width, 90 nm channel height and 20 nm gate length at Vdd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date. A higher beta ratio (beta> 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension

65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 /spl mu/m/sup 2/. Embedded DRAM cell size is 0.11 /spl mu/m/sup 2/. MOSFETs in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current. Furthermore poly-SiGe gate electrode and Ni Salicide were adopted to control high gate electrode activation and USJ (ultra shallow junctions) under low thermal budget. Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with non-slimming trim mask process were employed to achieve a small SRAM cell. Cu interconnects; using low-k dielectrics has an 180 nm pitch.

Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction

In this paper, the first systematic study of uniaxial stress effects on mobility (mu)/on-current (Ion) enhancement and gate current (Ig) reduction in FinFETs is described. We demonstrate for the first time that Ig of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher mu/Ion enhancement ratio by longitudinal strain and comparable/higher short-channel Idsat. Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.

Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

Vt variability in FinFET SRAM is evaluated for the first time by direct measurement of the cell transistors down to 25 nm gate length. By taking the V, mismatch between Pull-Down transistors (PD) or between PD & Pass Gate transistor (PG), the dependence of V, variability on the cell transistor layout and channel impurity concentration was clearly observed. Read / Write margins in FinFET SRAM cell are also investigated by measuring both N-curves and their variability. The results suggest that FinFET is still a promising candidate for SRAM applications even in 32 nm node and beyond, if the appropriate cell design is applied.

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

We discussed the optimization of structure and doping profile of bulk-FinFETs by using 3D process and device simulations. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. The analysis of stress field for bulk-FinFETs and SOI-FinFETs revealed that the channel stress induced by a stress liner (SL) in the bulk-FinFET is larger than that for the SOI-FinFET. In addition, we applied a raised source/drain (RSD) structure to the bulk-FinFETs and optimized doping profile in the RSD region. The combination of stress liner and RSD structure is found to be efficient for improving drive current of a bulk-FinFET

FinFET: the prospective multi-gate device for future SoC applications

This paper discusses the possibility of future large scale integration (LSI) of multi-gate device. FinFET is thought to he the most promising multi-gate device for LSI, because it easily realizes the self-aligned double-gate structure. At first, the feasibility of SRAM operation with FinFET in hp22 nm node is studied by simulation in terms of Vt fluctuation control. Next, it is demonstrated that FinFET on bulk Si substrate (bulk-FinFET) is a suitable candidate for cost-effective LSI manufacturing. The integration schemes of FinFET and planar FET on the same substrate are also developed for the fabrication of 128 Kbit SRAM ADM (array diagnostic monitor). Finally, successful SRAM cell operation is demonstrated with FinFET of Lg = 20 nm. Therefore, FinFET integrated circuit can provide a unique solution for future low-power SoC