Takeo Nakayama

World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS

Worlds first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor Ion/Ioff ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.

Advanced DSS MOSFET technology for ultrahigh performance applications

Dopant segregated Schottky MOSFET (DSS FET) is one of the key technologies which can improve the MOSFET performance thanks to reduction of external resistance and increase of carrier injection velocity. We have found that both laser spike annealing (LSA) and fluorine co-implant can reduce external resistance furthermore, which leads to boost drive currents of DSS FETs by 7% respectively. By optimizing these technologies, high drive currents of 1310 muA/mum and 1080 muA/mum at Ioff of 100 nA/mum are achieved at 1.0 V and 0.9 V respectively, without use of high-k/metal gate.

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.

A highly reliable interconnection for a BF + 2 -implanted junction utilizing a TiN/Ti barrier metal system

A submicrometer-rule interconnection structure of the Al-Si layer to the BF<inf>2</inf>⁺-implanted Si region is described. The contact resistance of Al-Si to BF<inf>2</inf>⁺-implanted Si increases more than those to B⁺- or As⁺-implanted Si, as contact hole size is scaled down to around 1 µ2. Through SEM and TEM analyses, it is found that solid phase epitaxial growth of Si takes place on the contact interfaces, where crystalline defects induced by BF<inf>2</inf>⁺implantation act as seeds. Thus, the effective metal contact area to Si is reduced very much. In order to realize a stable metallization system, a TiN/Ti barrier metal structure is introduced. The TiN/Ti structure is optimized in terms of contact resistance and contact barriers, and its feasibility for submicrometer-rule CMOS VLSIs is clarified.

0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node

For the fist time, low supply voltage SRAM operation with stress-enhanced dopant segregated Schottky (DSS) source/drain transistors is demonstrated. At constant SRAM cell current of 40 muA, we achieve two orders of magnitude lower bit-line leakage than conventional technologies at Vdd=0.7 V, while in case of constant bit-line leakage of 10 nA, supply voltage is successfully reduced down by 0.1 V. DSS technology is promising for low voltage SRAM operation for 32 nm node and beyond.

Accurate proximity correction method with total-process proximity-based correction factor (TCF)

A novel, accurate, one-dimensional process proximity correction method is proposed. The method is based on the relationship between a line width variation and the bias which should be corrected. This relationship is characterized by the Total process proximity-based Correction Factor (TCF) which is defined as the slope of the wafer CD variation curve to the mask design CD under a constant pattern pitch condition. At a TCF greater than 1, patterns should be corrected with values less than the line width deviation. By applying the new PPC method to 0.25 micrometer logic gate patterns, a correction rule table was experimentally obtained. The new PPC mask fabricated with the correction rule exhibited a significant improvement over the conventional correction technique in the logic device.

Excellent process control technology for highly manufacturable and high performance 0.18 /spl mu/m CMOS LSIs

Summary form only given. Highly manufacturable and high performance 0.18 /spl mu/m CMOS technology for logic LSIs with excellent process controllability has been proposed. N/sub 2/O based oxynitride process and OPC (Optical Proximity Correction) technology was developed and realized superior uniformity in CMOSFET characteristics. A new Ti salicide technology which was fine line effect free down to 0.15 /spl mu/m was also established. These technologies were demonstrated and verified by application to 0.18 /spl mu/m high performance logic LSI with high performance interconnects technology.