Akira Hokazono

Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling

Steep channel impurity-profiles formed by Si∶C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si∶C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.

Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond

Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-LG nMOSFET. Si:C layers work as the dopant-diffusion-barriers from the boron doped regions. Moreover, retrograde Halo profiles are also realized in this structure. Steep channel profiles at scaled device are confirmed, and the benefits of its profile at LG of 25 nm are discussed.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.

14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.

Evaluation of two-dimensional strain distribution by STEM/NBD.

We proposed a strain mapping technique by Nano Beam electron Diffraction (NBD) combined with an energy filter (EF) and a scanning transmission electron microscopy (STEM) function. The STEM function improves the accuracy of a position where a diffraction pattern is acquired. The EF excludes inelastic scattering and enables novel numerical processing for the appropriate measurement of distances between diffraction disks. Using this technique, strain distributions were measured for two different types of p-MOSFETs, i.e., source/drain regions of each MOSFET is composed of different types of silicide, and the difference of their strain distributions in the channel region was confirmed. The proposed method was able to clarify that the strain distributions are quite different depending on the silicide materials even if the exterior of the MOSFETs was almost identical.

Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth technique

High performance sub-100 nm MOSFETs have been realized utilizing elevated source/drain technologies. By utilizing the selective epitaxial growth process, the suppression of short channel effect, junction leakage current, and parasitic resistance are realized. Moreover, the necessity of special technique for channel engineering in order not to increase the gate-to-source/drain capacitance is described when using elevated source/drain structures. A novel prohibition process of deposition on poly-Si gate electrodes for reducing gate depletion is also mentioned.

Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation

A novel selective epitaxial growth (SEG) process that realizes a facet-free elevated source/drain (S/D) is proposed. The key points are the appropriate selection of the gate-sidewall material and its structural improvement. It was observed that the facet was not formed adjacent to SiN in contrast to the SiO2 case. Therefore, SiN is selected as a gate-sidewall. The novel gate-sidewall is constructed from a SiN sidewall and SiO2 liner layer which acts as a sidewall reactive ion etching (RIE) stopper. The SiO2 liner layer is lateral etched by wet treatment. By the SEG process, the facet, which is formed adjacent to the SiO2 liner is screened out within the lateral etched region, and no facet is observed along the SiN sidewall. Si lateral overgrowth on the shallow trench isolation (STI) region was also confirmed to be controllable in the facet-free SEG process. This novel SEG process was found to be successfully adapted to facet-free elevated S/D.

25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)

Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to form steep p-type channel profiles in n-channel MOS field-effect transistors (nMOSFETs) due to extremely low diffusivity of boron and indium in Si:C layers. This structure with low channel impurity improves mobility and suppresses threshold voltage (VTH) variation. Both items are essential for aggressively scaled MOSFETs with a gate length less than 25 nm. We demonstrated well-controlled, high-performance, and low VTH variability nMOSFETs with a Si:C-Si epitaxial channel structure.

Source/drain engineering for sub 100-nm technology node

ITRS2001 indicates 25-nm physical gate length and 10-17-nm extension depth are required in 65-nm technology node for high performance application. It means resultant requirement of precisely controlled conventional process and new material and process introduction. Though ion implantation and spike RTA are still base line technology for doping, it should be carefully optimized in process integration avoiding implantation-induced damage and transient enhanced diffusion. Careless process sequence might cause undesired enlargement of junction depth even in LPCVD temperature annealing. Sidewall scaling is also necessary to reduce source and drain parasitic resistance and it relates to the contact junctions and silicidation process. Cobalt salicide is widely used in recent technology node. However, its silicon consumption in silicidation process requires relatively deep contact junctions and tends to cause the interference of the contact junction to the channel region. Therefore, lower silicon consumption silicide material such as nickel SALICIDE is one of the solutions. NiSi silicidation can be performed at low temperature and silicon consumption is about 80% of CoSi2 silicide under the same silicide thickness condition. Additionally, more structural approach like elevated source/drain using selective silicon or silicon-germanium will be introduced to solve severer constraints.