Kiyoshi Ishikawa

Discrete Dopant Effects on Statistical Variation of Random Telegraph Signal Magnitude

This paper discusses the discrete channel dopant effects on the statistical variation of random telegraph signal (RTS) magnitude, which is defined by the threshold-voltage shift by RTS in MOSFETs. An analytical model for the statistical variation of RTS magnitude is presented. Considering discrete dopant effects, the RTS magnitude of MOSFETs exhibits a log-normal distribution, while the threshold voltage itself exhibits a normal distribution. The threshold-voltage shift by RTS will become a serious concern in 50-nm Flash memories and beyond.

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures

This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.

Impact of Shear Strain and Quantum Confinement on 110 Channel nMOSFET With High-Stress CESL

Numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along in terms of the device performance of strained 65nm-node nMOSFETs with Contact Etch Stop Layer (CESL), and that both the shear strain component and the quantum confinement effect play an important role in this superiority.

Modeling statistical distribution of random telegraph noise magnitude

Random telegraph noise (RTN) magnitude of MOSFETs is analyzed using three-dimensional device simulation taking random discrete dopant into account. The maximum RTN magnitude is inversely proportional to the RTN region area in which the surface potential is in the vicinity of its saddle point. The inverse of the maximum RTN magnitude exhibits a normal distribution.

Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation

A novel methodology is presented to generate the worst-case model including extraction of its compact model parameters. This method enables physically accurate worst-case prediction in the early stage of device development concurrently. It is found through the intensive TEG analysis and TCAD simulation that correlations between process factors have a significant impact on the worst-case corner estimation. A new extraction method of compact model parameters based on error propagation analysis is developed to consider correlations between parameters

Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current

We propose a compact model for flash memory cells that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary ELectron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130 nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories.

An analysis of the effect of hydrogen incorporation on electron traps in silicon nitride

The effect of hydrogen incorporation into nitrogen vacancies in silicon nitride on electron trap is analyzed using density functional theory method. A hydrogen atom is attached to a dangling bond which is well separated from other dangling bonds, whereas it is not attached to ones which strongly interact because of lattice distortion. An electron trap level caused by nitrogen vacancy becomes shallow by hydrogen incorporation. An electron is trapped in a deep level created by a silicon dangling bond before hydrogen incorporation, whereas it is trapped in a shallow level created by an anti-bonding state of a siliconsilicon bond after hydrogen incorporation. The simulation results qualitatively explain the experiment in which reduced hydrogen content in silicon nitride shows superior retention characteristics of the programmed state.

A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model

A design methodology optimizing constant-charge-injection programming (CCIP) for assist-gate (AG)-AND flash memories is proposed. Transient circuit simulations using an array-level model including lucky electron model (LEM) current source describing hot electron physics enables a concept design over the whole memory-string in advance of wafer manufacturing. The dynamic programming behaviors of various CCIP sequences, obtained by circuit simulations using the model is verified with the measurement results of 90-nm AG-AND flash memory, and we confirmed that the simulation results sufficiently agree with the measurement, considering the simulation results give optimum bias AG voltage approximately within 0.2V error. Then, we have applied the model to a conceptual design and have obtained optimum bit line capacitance value and CCIP sequence those are the most important issues involved in high-throughput programming for an AG-AND array.

Validation of the Effect of Full Stress Tensor in Hole Transport in Strained 65nm-Node pMOSFETs

We have developed a system consisting of a full-3D process simulator for stress calculation and k · p band calculation that takes into account the subband structure. Our simulations are in good agreement with the experimental data of strained Si-pMOSFETs of 65nm technology devices. This system is a powerful tool to optimize device structures with all stress components.

Modeling of Discrete Dopant Effects on Threshold Voltage Shift by Random Telegraph Signal

This paper discusses the discrete channel dopant effects on the threshold voltage shift by random telegraph signal (RTS) in MOSFETs. Appropriate grid spacing to incorporate discrete dopant effects in three dimensional device simulation is addressed to obtain consistent results with continuum limit. Considering discrete dopant effects, the threshold voltage shift of MOSFETs by RTS follows the log-normal distribution, while the threshold voltage itself follows the normal distribution. An analytical model for the distribution of the threshold voltage shift is also presented. The threshold voltage shift by RTS will become a serious concern in 50 nm flash memories and beyond