Katsumi Eikyu

Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis

A statistical compact RTN (Random Telegraph Noise) model with a fixed V<inf>th</inf> shift and V<inf>gs</inf> dependent trap time constants is proposed. It accurately reproduces the experimental observation of larger V<inf>th</inf> fluctuation at higher |V<inf>gs</inf>|. The model is also applied to analysis of SRAM V<inf>min</inf> fluctuation and finds out the distribution follows a log-normal statistics.

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Double offset-implanted source/drain extension and 550/spl deg/C silicon nitride deposition for sidewall and borderless contact have been applied to sub-0.1 /spl mu/m CMOS for improvement of short channel effect as well as parasitic resistance. Consequently, 830/400 /spl mu/A//spl mu/m drive current with 2.5 nm gate insulator has been achieved under 1 nA//spl mu/m off-leakage at 1.5 V operation with short channel tolerance to 80 nm gate length.

A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

This paper presents that advanced actively body-bias controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of static noise margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs are improved by the advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32nm and 49% for 22nm node. It is summarized that this technology is one of countermeasures for emerging generations.

Impact of Shear Strain and Quantum Confinement on 110 Channel nMOSFET With High-Stress CESL

Numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along in terms of the device performance of strained 65nm-node nMOSFETs with Contact Etch Stop Layer (CESL), and that both the shear strain component and the quantum confinement effect play an important role in this superiority.

Temperature Coefficient of Threshold Voltage in High-

The temperature coefficient of Vth (=dVth/dT), which is commonly utilized for circuit design, was systematically obtained against various TiN and capping layer thicknesses in high-k/metal gate field-effect transistors (FETs). It is known that the magnitude of |dVth/dT| for such FETs is larger than that of polycrystalline silicon (poly-Si) gate FETs. The origins of the dVth/dT difference among high-k/metal gate FETs were attributed to differences in the temperature coefficient of flat band voltage (=dVFB/dT) and the equivalent gate oxide thickness (EOT). Thicker TiN layers reduced dVFB/dT, which enlarged the magnitude of |dVth/dT|. The EOT increased as the TiN metal layer or Al2O3 capping layer increased in thickness. The large EOT led to an increase in |dVth/dT|, since dVth/dT is a function of the inverse of gate capacitance. In contrast, La2O3 capping hardly affected dVth/dT. This is because La2O3 capping did not affect EOT differently from Al2O3 capping. The relationship between dVth/dT and EOT implies that EOT scaling relieves the issue of large |dVth/dT| for high-k/metal gate FETs.

k

In this paper, we propose a new analytical electron mobility model in strained Si inversion layers suitable for implementation in a drift-diffusion simulator. Using our new model, a numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65-nm-node nMOSFETs with contact etch stop layer and that both the shear-strain component and the quantum confinement effect are key factors in contributing to this superiority.

Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

A novel methodology is presented to generate the worst-case model including extraction of its compact model parameters. This method enables physically accurate worst-case prediction in the early stage of device development concurrently. It is found through the intensive TEG analysis and TCAD simulation that correlations between process factors have a significant impact on the worst-case corner estimation. A new extraction method of compact model parameters based on error propagation analysis is developed to consider correlations between parameters

Impact of Shear Strain and Quantum Confinement on

The fabrication process of all-oxide layered structures of YBCO/PBCO/SrTiO3/PBCO/YBCO on MgO(100) substrates for superconductor-insulator-superconductor (SIS) tunnel junctions was investigated by in situ rf magnetron sputtering. Fully c-axis-oriented structure was obtained by varying the sputtering conditions. The optimized structure had a well-defined interface at each boundary between layers. A planar junction was fabricated by the atomic milling technique, and Josephson supercurrent and microwave response were observed. Moreover, a structure resembling an energy gap was found by differential resistance measurement.

\langle\hbox{110}\rangle

The very narrow mesa structures based on our 7th generation IGBT process are fabricated and it is found that the device with the narrowest mesa shows very poor short circuit (SC) withstand capability although it suppresses the conduction loss considerably. This poor SC capacity is caused by non-saturated output characteristics which are originated by collector bias induced barrier lowering in the middle of Si mesa. The current filamentation is observed in the 3D multi-cell short circuit simulation with self-heating and the SC capacity degradation due to the filamentation is enhanced in the narrower mesa structure.