Motoaki Tanizawa

Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis

A statistical compact RTN (Random Telegraph Noise) model with a fixed V<inf>th</inf> shift and V<inf>gs</inf> dependent trap time constants is proposed. It accurately reproduces the experimental observation of larger V<inf>th</inf> fluctuation at higher |V<inf>gs</inf>|. The model is also applied to analysis of SRAM V<inf>min</inf> fluctuation and finds out the distribution follows a log-normal statistics.

Direct measurement of stress dependent inversion layer mobility using a novel test structure

We propose a novel mobility measurement method which can be applied to industrial sized MOSFETs. The mobility variation caused by Shallow Trench Isolation (STI) stress is evaluated directly. Extracted piezoresistance coefficients in the inversion layer are close to their counterparts in bulk silicon. The stress effect model like that incorporated into BSIM4.3.0 is verified to adequately predict the behavior. Additionally, we have observed for the first time that the inversion layer mobility in <100> channel MOSFETs is less sensitive to the STI stress than that in <110> channel along MOSFETs. Therefore, CMOS devices with layouts the <100> direction is expected to have high performance with reduced source of design complication.

Impact of Shear Strain and Quantum Confinement on 110 Channel nMOSFET With High-Stress CESL

Numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along in terms of the device performance of strained 65nm-node nMOSFETs with Contact Etch Stop Layer (CESL), and that both the shear strain component and the quantum confinement effect play an important role in this superiority.

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.

Modeling statistical distribution of random telegraph noise magnitude

Random telegraph noise (RTN) magnitude of MOSFETs is analyzed using three-dimensional device simulation taking random discrete dopant into account. The maximum RTN magnitude is inversely proportional to the RTN region area in which the surface potential is in the vicinity of its saddle point. The inverse of the maximum RTN magnitude exhibits a normal distribution.

A surface potential model for bulk MOSFET which accurately reflects channel doping profile expelling fitting parameters

A surface potential model for bulk MOSFET which accurately reflects channel doping profile is proposed. Only physical parameters such as device structures and doping profiles are used in the proposed model. For the vertical direction to channel, the model consistently integrates both surface potential and arbitral channel doping profiles in Poisson equation by using HiSIM2 framework. For channel direction, the model improves Pangpsilas quasi-2D Gaussian box model by taking the effect of source/drain junction depth into account. To accurately reflect the effect of the doping profile, drain current is evaluated by numerical integration using the calculated surface potential. The dependence of both short channel effect (SCE) and the reverse short channel effect (RSCE) on Vds, Vbs, channel length, junction depth and channel doping profiles, are expressed accurately without using any fitting parameters.

Impact of Shear Strain and Quantum Confinement on

In this paper, we propose a new analytical electron mobility model in strained Si inversion layers suitable for implementation in a drift-diffusion simulator. Using our new model, a numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65-nm-node nMOSFETs with contact etch stop layer and that both the shear-strain component and the quantum confinement effect are key factors in contributing to this superiority.

\langle\hbox{110}\rangle

A novel methodology is presented to generate the worst-case model including extraction of its compact model parameters. This method enables physically accurate worst-case prediction in the early stage of device development concurrently. It is found through the intensive TEG analysis and TCAD simulation that correlations between process factors have a significant impact on the worst-case corner estimation. A new extraction method of compact model parameters based on error propagation analysis is developed to consider correlations between parameters

Channel nMOSFET With High-Stress CESL

The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability

Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation

We propose a compact model for flash memory cells that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary ELectron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130 nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories.