Yasuhiko Nitta
Mitsubishi
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Featured researches published by Yasuhiko Nitta.
international symposium on microarchitecture | 1993
Kazuo Nakamura; Narumi Sakashita; Yasuhiko Nitta; K. Shimomura; Takeshi Tokuda
Fuzzy inference, a data processing method based on the fuzzy theory that has found wide use in the control field, is reviewed. Consumer electronics, which accounts for most current applications of this concept, does not require very high speeds. Although software running on a conventional microprocessor can perform these inferences, high-speed control applications require much greater speeds. A fuzzy inference date processor that operates at 200000 fuzzy logic inferences per second and features 12-b input and 16-b output resolution is described.<<ETX>>
international solid-state circuits conference | 1996
Yasuhiko Nitta; Narumi Sakashita; K. Shimomura; F. Okuda; H. Shimano; S. Yamakawa; Akihiko Furukawa; K. Kise; H. Watanabe; Y. Toyoda; T. Fukada; M. Hasegawa; M. Tsukude; Kazutami Arimoto; S. Baba; Y. Tomita; S. Komori; Kazuo Kyuma; H. Abe
This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.
international solid-state circuits conference | 1993
Kazuo Nakamura; Narumi Sakashita; Yasuhiko Nitta; K. Shimomura; Takio Ohno; K. Eguchi; Takeshi Tokuda
A fuzzy inference processor that performs fuzzy inference with 12-b resolution input at 200 kFLIPS (fuzzy logical inferences per second) is described. Three techniques are adopted to attain this performance: (1) membership-function generators constructed of combinational logic, which calculate a membership-function value in less than half of a clock cycle; (2) rule instructions that execute one-rule-by-one instruction in an antecedent unit; and (3) an improved add/divide algorithm that calculates a centroid in a consequent unit. The block diagram of this processor is shown. The chip, fabricated by 1- mu m single-polycide, double-metal CMOS technology, contains 86-k transistors in a 7.5-mm*6.7-mm die, and is packaged in an 80-pin flat package. The chip operates at more than 20-MHz clock frequency at 5 V.<<ETX>>
Archive | 1996
Yasuhiko Nitta; Masaki Tsukude
Archive | 1999
Yasuhiko Nitta; Junichi Kondo
Archive | 1988
Yasuhiko Nitta; Kazuo Nakamura
Archive | 2001
Yasuhiko Nitta; Hiroki Takahashi
Archive | 1996
Yasuhiko Nitta; Narumi Sakashita; Fumihiro Okuda; Hiroki Shimano; Satoshi Yamakawa; Akihiko Furukawa; Koji Kise; Tetsuo Fukada; Makiko Hasegawa; Kazutami Arimoto; Shinji Babaz; Kazuo Kyuma; Haruhiko Abe
Archive | 1995
Yasuhiko Nitta; Narumi Sakashita; K. Shimomura; Shinji Komori
Archive | 1993
Kazuo Nakamura; Narumi Sakashita; Yasuhiko Nitta; Takeshi Tokuda