Takushi Hashida

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1-3], designing clock-generating circuits for the receiver front-end is a significant challenge. In a phase interpolator (PI) commonly used in conventional receivers for a multi-channel configuration, both the linearity and frequency characteristics of the circuit affect the interpolation accuracy since it dynamically interpolates between reference clock signals supplied from a PLL, making the design more difficult. Blind-clock ADC-based receivers [4] eliminate the need for a clock-phase-adjusting circuit, but the area and power overheads are large due to high-sampling-rate ADCs. To address these issues, we fabricate and test a 28nm CMOS blind-clock receiver that performs phase tracking by using a data interpolator (DI). We confirm error-free operation of the receiver up to 32Gb/s with power consumption of 308.4mW from a 0.9V power supply.

Managing Non-Volatile Memory in Database Systems

Non-volatile memory (NVM) is a new storage technology that combines the performance and byte addressability of DRAM with the persistence of traditional storage devices like flash (SSD). While these properties make NVM highly promising, it is not yet clear how to best integrate NVM into the storage layer of modern database systems. Two system designs have been proposed. The first is to use NVM exclusively, i.e., to store all data and index structures on it. However, because NVM has a higher latency than DRAM, this design can be less efficient than main-memory database systems. For this reason, the second approach uses a page-based DRAM cache in front of NVM. This approach, however, does not utilize the byte addressability of NVM and, as a result, accessing an uncached tuple on NVM requires retrieving an entire page. In this work, we evaluate these two approaches and compare them with in-memory databases as well as more traditional buffer managers that use main memory as a cache in front of SSDs. This allows us to determine how much performance gain can be expected from NVM. We also propose a lightweight storage manager that simultaneously supports DRAM, NVM, and flash. Our design utilizes the byte addressability of NVM and uses it as an additional caching layer that improves performance without losing the benefits from the even faster DRAM and the large capacities of SSDs.

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-time linear equalizer and a two-tap loop unrolled DFE using adjustable-threshold comparators. The receiver occupies 0.24 mm2 and consumes 308.4 mW from a 0.9-V supply when it is implemented with a 28-nm CMOS process.

Extending postgreSQL to handle OLXP workloads

The importance of database systems to efficiently support OLTP and OLAP mixed workloads, the so-called OLXP workloads, has been recognized recently. Some research projects and also some commercial database systems with focus on the processing of OLXP workloads have appeared in the last few years. In this paper, we present our work to extend the PostgreSQL OSS database system to efficiently handle OLXP workloads. Besides PostgreSQLs traditional OLTP-oriented row data store, we provide a new OLAP-oriented column data store in the form of a new index. Unlike previous works that support both row and column data stores, we propose a column index with no restrictions concerning data size and/or updatability. Therefore, transactional data inserted to PostgreSQL row data store become immediately available for efficient analytical processing using the proposed column store index.

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm2 and consumes 609.9 mW of power from a 0.9-V supply.

Design of a Shared Memory mechanism for efficient paralell processing in PostgreSQL

PostgreSQL is a reliable and mature OSS RDBMS that has become widely utilized in enterprise systems recently. In order to meet the increasing performance requirements of such systems, PostgreSQL OSS Community enforced PostgreSQL version 9.4 parallel execution framework introducing the Dynamic Shared Memory and the Dynamic Background Workers. However, the Dynamic Shared Memory does not guarantee that shared data are mapped to the same address space in the processes and thus data with pointers cannot be straightly shared without local copies. In this paper we propose a new shared memory framework called Shared MemoryContext that provides a shared memory mapped to the same address to all processes. It enables an efficient parallel processing in PostgreSQL by avoiding unnecessary data copies of inter-process shared data. The Shared MemoryContext interface is compatible with PostgreSQLs MemoryContext interface and thus existing PostgreSQL routines can be used for parallel processing without modification.