Takuya Arafune

Timing measurement BOST with multi-bit delta-sigma TDC

This paper describes design and implementation of a multi-bit delta-sigma (ΔΣ) Time-to-Digital Converter (TDC) with Data-Weighted-Averaging (DWA) algorithm on analog FPGA. I/O interfacing circuits such as double-data-rate (DDR) memory interfaces are very important, and their low-cost, high-quality test is challenging. We propose here simple test circuitry for measuring digital signal timing of I/O interfacing circuits with high resolution and good accuracy. We focus on TDC applications of ΔΣmodulators (for fine-timing-resolution, digital output, and simple circuitry) and with multi-bit architecture (for short testing time). However, the multi-bit ΔΣ TDC suffers from delay mismatches among delay cells. Then we propose to apply the DWA algorithm for the delay cells in order to solve this problem. Our experimental results showed that the DWA algorithm improved the overall multi-bitΔΣ TDC linearity.

SAR ADC design using Golden ratio weight algorithm

This paper describes redundant successive approximation register (SAR) ADC design methods which enable high-reliability and high-speed AD conversion using digital error correction. Especially we propose to apply Fibonacci sequence and its property called Golden ratio to SAR ADC design to optimize redundant search algorithms. We present some interesting properties for well-balanced redundant SAR ADC design, as well as golden-ratio-weighted DAC topologies for its internal usage.

Fibonacci sequence weighted SAR ADC algorithm and its DAC topology

This paper describes redundant successive approximation register (SAR) ADC design methods to improve reliability and conversion speed by digital error correction. Especially we show that redundant SAR ADC using Fibonacci sequence and its property called Golden ratio can be well-balanced design. We also present some simple golden-ratio-weighted DAC topologies for easy realization of the redundant SAR ADC by utilizing many interesting properties of Fibonacci sequence.

Single-inductor dual-output soft-switching converter with voltage-mode resonant switch

This paper presents our study on the soft-switching converters with voltage-mode. The switching converters are well-known to obtain high efficiency, but their resonant voltages of the voltage-mode converters go very high. We propose here a soft-switching converter with the clamp circuit in order to reduce the peak voltages. We have investigated the difference of the characteristics with/without the clamp circuit for both half/full-wave converters in simulation. Further, we have investigated a single-inductor dual-output converter in order to reduce the number of the resonant parts.

Selectable notch frequencies of EMI spread spectrum using pulse modulation in switching converter

This paper proposes a novel EMI spread spectrum technique to enable to set notch frequencies using pulse modulation in switching converters. The notches appear at the frequencies obtained from empirically derived equations with the proposed spread spectrum technique using the pulse coding methods, the PWM (Pulse Width Modulation) coding or the PCM (Pulse Code Modulation) coding. This technique would be useful for the communication equipment which receives standard radio waves, without being affected by noise from the switching converters. In our proposed technique, the notch frequencies in the spread spectrum depend on the pulse coding method. We have investigated this technique to apply to the switching converters and found that there is good relationship agreement between the notch frequencies and the empirical equations. The notch frequency in the PWM coding is equal to the equation F=k/(WM-Wo). In the PCM coding, that is equal to the equation F=k/(TM-To).