Takuya Ozaki

50 nm gate electrode patterning using a neutral-beam etching system

A 50-nm-width metal-oxide-semiconductor (MOS) gate etching process was established using a recently-developed neutral-beam etching system by optimizing the gas chemistry and the electrode bias condition. In a comparison with poly-Si gate etching using either SF6 or Cl2 gas chemistries, opposite etching characteristics were observed in the pattern profile. Consequently, the use of a mixture of these gases was proposed in order to achieve fine control of the etching profiles. The energy of the neutral beam was increased by applying a 600 kHz rf bias to the bottom electrode. The rf bias was very effective in increasing the etch rate and the anisotropy of the poly-Si gates, with no deterioration of the neutralization efficiency. The oxide leakage current achieved for a MOS capacitor etched by the neutral beam was one order of magnitude lower than that achieved by conventional plasma etching.

Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching (NBE). NBE can completely eliminate the charge build-up and photon-radiation damages caused by the plasma. The fabricated FinFETs realize a higher device performance (i.e., higher electron mobility) than that obtained by using a conventional reactive-ion etching. The improved mobility is well explained by the NB-etched atomically flat surface. These results strongly support the effectiveness of the NB technology for nanoscale CMOS fabrication

Highly selective low-damage processes using advanced neutral beams for porous low-k films

A highly selective and low-damage damascene process for porous methyl-silsesquioxane (porous MSQ, k-2.2) films has been realized using a neutral beam system we have developed. Use of a SF6 or CF4 neutral beam enables etching of porous MSQ with higher selectivity to the photoresist than what can be obtained in a conventional plasma. This is considered to be because the neutral beam eliminates exposure to ultraviolet (UV) light which enhances the resist etching. Anisotropic, low-dimension-shift damascene etching of porous MSQ is achieved through the neutral beam system. In addition, an O2 neutral beam reduces damage to the sidewall of porous MSQ during the resist ashing process. Also, a modified layer generated on porous MSQ during ashing using a H2 or H2∕N2 beam could prevent damage by UV light, which allows more effective resist ashing in a dual damascene structure of porous MSQ. Accordingly, this neutral beam system is a promising candidate for use in porous MSQ damascene processes.

Damage-free neutral beam etching technology for high mobility FinFETs

Our newly developed neutral beam (NB) etching accomplished the damage-free (defect-free and smooth surface) fabrication of high aspect rectangular Si-fins for the first time. The fabricated FinFETs realized higher device performance (higher electron mobility) than that using a conventional reactive ion etching. The improved mobility is well explained by the NB etched atomically-flat surface. Our new results strongly support the effectiveness of the NB technology for the nano-scale CMOS fabrication

Fabrication of a Vertical-Channel Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Using a Neutral Beam Etching

A vertical ultrathin-channel (UTC) formation process using a low-energy neutral beam etching (NBE) for a double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed for the first time. The NBE can perfectly eliminate the charge build-up and photon radiation damages from the plasma. By utilizing the NBE, fin-type vertical MOSFETs with damage-less smooth sidewalls were successfully fabricated. The fabricated FinFETs realized higher electron mobility than that using a conventional reactive ion etching. The improved mobility is well explained by the atomically-flat surface utilizing by the NBE.

Highly anisotropic gate electrode patterning in neutral beam etching using F2 gas chemistry

Pure F2 gas chemistry was evaluated in comparison with SF6 and Cl2 gas chemistries for etching poly-Si gates of metal-oxide-semiconductor field effect transistors in our neutral beam source. In the case of SF6 gas chemistry, the polycrystalline silicon (poly-Si) etch rate was high enough, whereas a large side etching was observed. In the case of Cl2 gas chemistry, the pattern profile was anisotropic, but the etch rate was very low. The tradeoff was caused by differences in the etching reactivity of F and Cl radicals with the poly-Si. Though the SF6-based neutral beam caused a large side etching due to diffused F radicals, an anisotropic profile was obtained by using the F2-based neutral beam, and the etch rate was much larger than that in the Cl2 gas chemistry. These notable characteristics were accomplished by suppressing excessive dissociation of F radicals and by generating large amount of negative F ions in a pulse-time-modulated F2 plasma in the neutral beam source.

Damage-free metal-oxide-semiconductor gate electrode patterning on thin HfSiON film using neutral beam etching

The charging damage of metal-oxide-semiconductor (MOS) capacitors and the degradation of HfSiON dielectric films during gate electrode etching were compared with neutral beam etching and conventional plasma etching. Furthermore, residual flux of charged particles (positive/negative ions and electrons) in the neutral beam was analyzed and the relationship between the residual charge flux and the charging damage induced in SiO2 and/or HfSiON gate dielectrics was investigated. Although the residual charge flux and its composition varied depending on the neutral beam acceleration method (dc or rf biasing), the amounts were noticeably lower than that with the plasma etching system. The gate leakage currents of the MOS capacitors etched using the neutral beam were sufficiently lower than those in the plasma etching, which was consistent with the charge flux during the gate electrode etching. On the neutral beam irradiated surface of the HfSiON film, there were no changes in the x-ray photoelectron spectrometry ...

Characterization of neutral beam source based on pulsed inductively coupled discharge: Time evolution of ion fluxes entering neutralizer

Low-energy neutral beam sources are very promising candidates for realization of next generation ultralarge-scale integrated devices. The use of pulsed inductively coupled plasma and surface (wall) neutralizer appears to be an efficient way of producing high-flux low-energy neutral beams. Measurement of the time evolution of ion fluxes entering the neutralizer plays an essential role in understanding and control of these neutral beam systems. Here the authors present a simple method for measuring the temporal dynamics of ion fluxes in neutral beam source described elsewhere [S. Samukawa et al., J. Vac. Sci. Technol. A 20, 1566 (2002)]. The method is based on the use of a low aspect ratio orifice in the center of neutralizer, magnetic filter, and Faraday cup. At some conditions, it allows (1) to measure the magnitudes of positive and negative wall ion fluxes in pulsed plasmas with an extremely high temporal resolution (better than 1μs) and (2) to examine the difference in surface neutralization between pos...

New Fabrication Technology of Fin Field Effect Transistors Using Neutral-Beam Etching

Ultrathin-channel formation of a vertical-type double-gate metal oxide semiconductor field effect transistor using a low-energy neutral-beam etching (NBE) is proposed. The NBE can completely eliminate charge buildup and photon radiation damage from the plasma. By optimizing NBE conditions, rectangular vertical channels were fabricated with a SiO2 hard mask under low-energy NBE conditions.