Thomas E. Tang

An 0.8µm CMOS technology for high performance logic applications

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

VLSI Local interconnect level using titanium nitride

A local interconnect technology has been developed for VLSI CMOS applications using a titanium nitride layer. The technology has been realized by utilizing the titanium nitride layer that forms during the self-aligned titanium silicide process: which is used to simultanously reduce gate and junction sheet resistances to < 1 ohm/sq. Normally the TiN layer is discarded, but in this process the 0.1µm thick TiN layer is patterned and etched to provide local connections between gates and N+ and P+ junctions, with a sheet resistance of < 10 ohm/sq. This is accomplished without area consuming contacts or metal straps, and without any additional deposition steps, in addition to providing a VLSI version of the buried contact process, the technology results in self-aligned contacts and minimum geometry junctions, for reduced capacitance. The technology has been demonstrated by the fabrication of a CMOS VLSI memory with nearly half a million 1µm transistors.

In-situ doped polysilicon using vapor dopant for high density DRAMs

A highly conformal LPCVD (low-pressure chemical vapor deposition) in-situ doped (ISD) polysilicon process, using a low-toxicity vapor dopant source, t-butylphosphine (TBP), is developed in a standard automated horizontal LPCVD furnace for prototyping 16-Mb DRAMs (dynamic RAMs). The dopant incorporation is found to increase with increasing TBP concentration and decreasing deposition temperature. However, the conformality of the ISD polysilicon decreases with increasing dopant incorporation. A 700 degrees C anneal is sufficient to activate the dopant. An optimized condition gives uniform deposition over a 75-wafer load with a resistivity less than 1.0 m Omega -cm and a side/top step coverage better than 97%. It can fill 10- mu m-deep, 0.8- by 1.5- mu m-wide trenches without forming any voids.<<ETX>>