Thomas Witters
Katholieke Universiteit Leuven
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Featured researches published by Thomas Witters.
Applied Physics Letters | 2005
Chao Zhao; Thomas Witters; Bert Brijs; Hugo Bender; O. Richard; Matty Caymax; J. Schubert; V. V. Afanas’ev; Andre Stesmans; D. G. Schlom
Ternary oxides, GdScO3, DyScO3, and LaScO3, deposited by pulsed laser deposition using ceramics targets of stoichiometric composition, were studied as alternative high-k gate dielectrics on (100) Si. Their physical characterization was done using Rutherford backscattering, spectroscopic ellipsometry, x-ray diffraction, and transmission electron microscopy on blanket layers deposited on (100) Si, and electrical characterization on capacitors. It is found that DyScO3 and GdScO3 preserve their amorphous phases up to 1000°C. Other encouraging properties for high k applications were demonstrated, including k-value ∼22, almost no hysteresis or frequency dispersion in C–V curves, and leakage current reduction comparable to that of HfO2 of the same equivalent oxide thickness.
electronic components and technology conference | 2011
Augusto Redolfi; Dimitrios Velenis; Sarasvathi Thangaraju; P. Nolmans; Patrick Jaenen; M. Kostermans; U. Baier; E. Van Besien; Harold Dekkers; Thomas Witters; Nicolas Jourdan; A. Van Ammel; Kevin Vandersmissen; Simon Rodet; Harold Philipsen; Alex Radisic; Nancy Heylen; Youssef Travaly; Bart Swinnen; Eric Beyne
The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.
Journal of The Electrochemical Society | 2006
S. Van Elshocht; P. Lehnen; B. Seitzinger; A. Abrutis; C. Adelmann; Bert Brijs; Matty Caymax; Thierry Conard; S. De Gendt; Alexis Franquet; C. Lohe; M. Lukosius; Alain Moussa; O. Richard; P. Williams; Thomas Witters; Paul Zimmerman; Marc Heyns
Rare-earth scandate materials have been identified as candidates for gate dielectrics in metal oxide semiconductor transistors because of their high thermal stability against crystallization in combination with a high-dielectric constant. In this study, tris(1-methoxy-2-methyl-2-propoxy)dysprosium [Dy(mmp) 3 ] and Sc(mmp) 3 are evaluated as metallorganic chemical vapor deposition precursors for deposition of Dy x Sc y O z on silicon at moderate temperatures (450-600°C). These temperatures allow easy integration into a standard transistor flow. The layers are uniform with a close to bulk density and smooth top surface. Electrical characterization measurements shows a gate leakage current of 1.8 X 10 -5 A/cm 2 at 4.5 V for an equivalent oxide thickness of 2.0 nm. Limited hysteresis (9 mV) and frequency dispersion (3% difference in accumulation capacitance between 10 and 250 kHz) was observed.
international electron devices meeting | 2014
Leqi Zhang; Bogdan Govoreanu; Augusto Redolfi; Davide Crotti; Hubert Hody; Vasile Paraschiv; Stefan Cosemans; Christoph Adelmann; Thomas Witters; Sergiu Clima; Yangyin Chen; Paul Hendrickx; Dirk Wouters; Guido Groeseneken; Malgorzata Jurczak
An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.
international electron devices meeting | 2007
S. Kubicek; Tom Schram; V. Paraschiv; Rita Vos; Marc Demand; C. Adelmann; Thomas Witters; Laura Nyns; Lars-Ake Ragnarsson; H.Y. Yu; A. Veloso; R. Singanamalla; Thomas Kauerauf; Erika Rohr; S. Brus; C. Vrancken; V. S. Chang; R. Mitsuhashi; A. Akheyar; Hyunyoon Cho; Jacob Hooker; Barry O'Sullivan; T. Chiarella; C. Kerner; Annelies Delabie; S. Van Elshocht; K. De Meyer; S. De Gendt; P. Absil; Thomas Hoffmann
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.
symposium on vlsi technology | 2014
Ludovic Goux; Andrea Fantini; A. Redolfi; Chao-Yang Chen; F.F. Shi; Robin Degraeve; Yangyin Chen; Thomas Witters; Guido Groeseneken; Malgorzata Jurczak
We engineer a scalable and CMOS-friendly RRAM stack using down to 3nm ALD-based Ta<sub>2</sub>O<sub>5</sub>. The 20nm-sized TiN\Ta<sub>2</sub>O<sub>5</sub>\Ta device operated at 50μA exhibits ultra-fast write (~5ns) at moderate voltage (<;2V) with >10<sup>9</sup> write endurance. We also demonstrate excellent disturb and retention characteristics, which we relate to the appropriate tuning of the oxygen chemical-potential profile along the filament by means of the Ta scavenger material and thickness.
symposium on vlsi technology | 2008
Tom Schram; S. Kubicek; Erika Rohr; S. Brus; C. Vrancken; S.Z. Chang; V. S. Chang; R. Mitsuhashi; Y. Okuno; A. Akheyar; Hyoun-Myoung Cho; Jacob Hooker; V. Paraschiv; Rita Vos; F. Sebai; Monique Ercken; P. Kelkar; Annelies Delabie; C. Adelmann; Thomas Witters; Lars-Ake Ragnarsson; C. Kerner; T. Chiarella; Marc Aoulaiche; Moonju Cho; Thomas Kauerauf; K. De Meyer; A. Lauwers; T. Hoffmann; P. Absil
We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La<sub>2</sub>O<sub>3</sub>, Dy<sub>2</sub>O<sub>3</sub> and Al<sub>2</sub>O<sub>3</sub> on both HfSiO(N) and SiO<sub>2</sub> to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).
Journal of The Electrochemical Society | 2004
Sven Van Elshocht; Mikhail R. Baklanov; Bert Brijs; Richard Carter; Matty Caymax; L. Carbonell; Martine Claes; Thierry Conard; Vincent Cosnier; Lucien Date; Stefan De Gendt; J. Kluth; Didier Pique; Olivier Richard; Danielle Vanhaeren; Guy Vereecke; Thomas Witters; Chao Zhao; Marc Heyns
The physical bulk properties of metalorganic chemical vapor deposited (MOCVD) deposited HfO 2 layers were characterized as a function of deposition temperature. thickness, and starting surface. It is shown that depositing HfO 2 layers at 300°C results in a lower density film compared to films deposited at higher temperature (e.g., 485 and 600°C). In addition, it is shown that layers deposited at 300°C contain significant amounts of carbon originating from the organic precursor (tetrakis-diethylamidohafnium). As a result of the low density and/or carbon contamination, the dielectric properties of these layers are very poor. It is observed that the density of the film is heavily dependent on the thickness, where very thin layers have a density that is only a fraction of the bulk density regardless of the deposition temperature. For thicker layers, a higher deposition temperature is seen to result in a higher density, although still lower than bulk density, as observed by ellipsometric porosimetry. Finally, the crystalline state of the material is found to be dependent on the deposition temperature, thickness, and post-deposition anneal. Based on our results, MOCVD deposited HfO 2 layers are expected to be polycrystalline and present in its cubic and/or monoclinic phase.
symposium on vlsi technology | 2008
S. Kubicek; Tom Schram; Erika Rohr; V. Paraschiv; Rita Vos; Marc Demand; C. Adelmann; Thomas Witters; Laura Nyns; Annelies Delabie; Lars-Ake Ragnarsson; T. Chiarella; C. Kerner; Abdelkarim Mercha; B. Parvais; Marc Aoulaiche; C. Ortolland; H.Y. Yu; A. Veloso; Liesbeth Witters; R. Singanamalla; Thomas Kauerauf; S. Brus; C. Vrancken; Vincent S. Chang; Shou-Zen Chang; R. Mitsuhashi; Y. Okuno; A. Akheyar; Hyunyoon Cho
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.
Japanese Journal of Applied Physics | 2013
A. Veloso; Soon Aik Chew; Yuichi Higuchi; Lars-Ake Ragnarsson; Eddy Simoen; Tom Schram; Thomas Witters; Annemie Van Ammel; Harold Dekkers; Hilde Tielens; K. Devriendt; Nancy Heylen; F. Sebaai; S. Brus; Paola Favia; Jef Geypen; Hugo Bender; A. Phatak; Michael S. Chen; Xinliang Lu; Seshadri Ganguli; Yu Lei; Wei Tang; Xinyu Fu; Srinivas Gandikota; Atif Noori; Adam Brand; Naomi Yoshida; Aaron Thean; Naoto Horiguchi
This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.