Erika Rohr

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO₂ based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T_inv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I_off=100 nA/μm with V_DD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V_T of 0.3/-0.4V, good V_T-uniformity, and V_T-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

LASER-ASSISTED REMOVAL OF PARTICLES ON SILICON WAFERS

Laser cleaning is one of the new promising dry cleaning techniques considered by semiconductor companies to replace wet cleans in the near future. A dry laser cleaning tool was tested that uses an inert gas jet to remove particles lifted off by the action of a DUV excimer laser. A model was developed to simulate the cleaning process and analyze the influence of experimental parameters on laser cleaning efficiency. The best cleaning efficiencies obtained with 1.0 μm SiO2, ∼0.3 μm Si3N4, and 0.3 μm SiO2 particles deposited on Si wafers were 84±8%, 33±4%, and 12±7%, respectively. This is in qualitative agreement with theoretical calculations showing the existence of a size threshold for the removal of nonabsorbing particles by dry laser cleaning. Among the process parameters tested to optimize the process efficiency, fluence showed the highest influence on removal efficiency, before the number of laser pulses and the laser repetition rate. The use of high fluences was limited by the damaging of the wafer sur...

8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS

We report low V<inf>t</inf> (V<inf>t,Lg=1µm</inf>=±0.26V) high performance CMOS devices with ultra-scaled T<inf>inv</inf> down to T<inf>inv</inf>∼8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T<inf>inv</inf> (2) 220mV lower long channel pMOS V<inf>t</inf> (3) 21%/12% pMOS/nMOS drive current increase at I<inf>off</inf>=100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T<inf>inv</inf> of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

Challenges with Respect to High-k/Metal Gate Stack Etching and Cleaning

Novel high-k gate dielectrics (HK), often Hf-based oxides, are considered for the 45 nm node and beyond to allow further scaling of the gate dielectric. In order to prevent Fermi-level pinning, metal gates (MG) with the proper work function have to be used on the high-k dielectrics. These can be implemented in a Dual MG approach [1] where thin metal layers are inserted between the high-k and the poly-Si electrode during gate stack formation (see Figure 1 left). In addition, the work function can be further tuned through high-k cap layers in high-k cap inserted CMOS (see Figure 1 right) [2,3]. Other options are ‘metal gate last’ schemes where a dummy poly-Si gate is replaced by metal after formation of the NMOS and PMOS on the wafer or, alternatively, if Fully Silicided (FUSI) gates are used (see Figure 2).

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

The effects of ultrathin EOT on the carrier mobility in bulk-Si, UTBOX-FDSOI and SiGe-QW pFET devices were compared. The mobility is found to decrease dramatically with the EOT (Tinv) as a result of stronger charge and surface roughness scattering at thinner SiOx interface layers irrespective of the device technology. UTBOX-FDSOI and bulk-Si nFETs have identical mobility values (190 cm2/Vs) at Tinv=12.5Å. In the UTBOX-FDSOI device architecture, a positive back gate bias provides a strong enhancement in electron mobility. In SiGe-QW pFET devices, a 150% improvement in hole-mobility is observed with low thermal budget laser-anneal (LA).

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si<inf>45</inf>Ge<inf>55</inf>/Si cap deposition and the workfunction metal, high performance devices with balanced V<inf>t,sat</inf> (+0.12V, −0.16V) at scaled T<inf>inv</inf>∼1nm and gate length L<inf>g</inf>∼30nm are reported, leading to 17ps ring oscillators at 1µW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

Implementing cubic-phase HfO 2 with κ-value ∼ 30 in low-V T replacement gate pMOS devices for improved EOT-Scaling and reliability

Higher κ-value HfO₂ (κ~30) was evaluated in replacement metal gate pMOS devices. The higher-κ was achieved by doping and anneal of the HfO₂ causing crystallization into the cubic phase. The resulting gate-stack has up to 10³ × lower gate-leakage current compared to a reference HfO₂: J_G at -1 V ~ 2 μA/cm² at EOT~9.7 Å. The better J_G - EOT-scaling, result in performance and reliability improvements when normalized to the J_G.

Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.