Timothy G. McNamara

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor

High frequency microprocessor designs require rigorous design guidelines, design methodology advancements, and novel approaches in circuit design style for processors operating in the high megahertz range. Timing closure becomes the single most important design issue, however other design metrics such as area, power and noise need to be given equal consideration within the design cycle. Custom design techniques were used through out the logic circuits and arrays as well as the overall design planning for the 500 MHz microprocessor cycle time.

An advanced optical diagnostic technique of IBM z990 eServer microprocessor

In this paper, we describe an advanced optical diagnostic technique used for diagnosing the IBM z990 eServer microprocessor (Slegel et al., 2004). Time-to-market pressure demands quick diagnostic turnaround time and high diagnostic resolution while the ever increasing design complexity, density, cycle time, and shrinking technologies dramatically add difficulties to diagnostics. Although design-for-test (DFT) and design-for-diagnostics (DFD) features are implemented in the latest microprocessors to help easing the diagnostic efforts, they may still not be sufficient to diagnose certain fails. The well-known picosecond imaging circuit analysis (PICA) (Kash and Tsang, 1997) tool, equipped with the high quantum efficiency superconducting single-photon detector (SSPD,) shows a unique diagnostic capability for optically probing the internal nodes of a chip. Several hard-to-diagnose examples will be used to demonstrate the unique capabilities of this technique

PLL modeling and verification in a cycle-simulation environment

Recent advances in technology, computer architecture, and automated design environments have ushered in a new era of computer design in which large complex servers such as the S/390 G5 Parallel Enterprise Server™ can be delivered with times to market once reserved for low-end systems such as single-user workstations and personal computers. Yet, the time to market is inversely proportional to customer demand for reliable and continuously available systems. Therefore, the need exists to build and simulate a complete system which incorporates realistic and accurate behavioral representations for all design components. This paper describes a method for modeling an analog phase-locked loop, interfacing it with digital sequential logic components, and simulating the entire system in a high-performance two-cycle simulation environment. Further discussion demonstrates the role this verification has played in the deployment of an improved design point with a shorter time to market compared to previous generations of S/390® CMOS machines.