Tina Wagner

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

Methodology for balancing design and process tradeoffs for deep-subwavelength technologies

For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of model-based simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e.g., between overall chip density and manufacturing cost and yield. The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.

Yield optimization for third party library elements

Optimization of semiconductor product yield requires control of systematic defects. A variety of industry tools are available to check designs for systematic layouts that will be difficult to manufacture. Because of the cost associated with setting up the rules for a checking tool and the cost of licenses needed to evaluate designs, manufacturing process lines typically enable a limited set of tools to evaluate designs for systematic yield sensitivity. Semiconductor product design systems typically incorporate library elements designed by third party design companies. When third party library suppliers do not have access to the licenses or expertise to use the tools selected by the target manufacturing line, a barrier is created to having all library elements in a semiconductor design system checked to the same level. This results in a yield exposure for library elements that are not evaluated and fixed. This paper describes a method used to enable systematic yield evaluation for 32nm library elements procured from third party library suppliers. The third party library supplier provides layout data to the contracting library owner for yield sensitivity analysis. Changes are prioritized and fed back to the third party library supplier. This method interlocks design practices with the third party library supplier and provides a means for the contracting library owner to evaluate third party library elements and provide feedback to optimize the design.