Stephen E. Greco

Predicting substrate-induced focus error

The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process.

Hotspot detection and design recommendation using silicon calibrated CMP model

Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for todays designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

Understanding, modeling, and detecting pooling hotspots in copper CMP

Multi-step Chemical Mechanical Polishing (CMP) has been used in copper interconnect fabrication for more than a decade. During this time, advances in both the CMP-based damascene manufacturing processes and in the design flows, have enabled significant uniformity improvements for both metal thickness and surface topography, producing corresponding improvements in parametric and functional yields and enabling smaller process nodes. However, improving post CMP planarity and widening CMP process windows have lead to an increased risk of functional yield failures due to copper pooling (sometimes called puddling). These failures occur when the overburden copper and/or barrier material is not cleared during CMP, producing an electrical short between two neighboring lines. We first sought to understand the source of this failure mode, based on recently reported research and data trends seen in state of the art copper CMP manufacturing processes. Once copper pooling mechanisms were identified, CMP models were enhanced to more accurately predict pooling hotspot locations. These models can be used to improve CMP process optimization and/or Design for Manufacturing (DFM) based flows that detect and remove pooling hotspots.

193 lithography and RELACS processing for BEOL lithography

This paper presents data obtained in developing a process using 193 nm lithography and the RELACS contact hole shrink technique. For the line/space levels, process windows showing resist performance using chrome on glass masks are presented. Data showing feature size linearity and the requirements for optical proximity correction (OPC) are presented. Some of the OPC trends observed are discussed and compared to results obtained using 248 nm lithography. Image shortening data also compares the results obtained in 193 and 248 lithography. Etch results for the new 193 resists are given and show the etch resistance of this relatively new class of photoresist materials. For contact hole and via levels, results using 193 lithography and COG masks show the importance of the mask error enhancement factor (MEEF), print bias and resolution. Due to the relative immaturity and performance of contact hole resists for 193 lithography, Clariants RELACS process was investigated with 248 nm resists. In this process contact holes are printed larger than required and then reduced to the desired size by a chemical shrink process. Results obtained with 248 lithography using state of the art resists and phase shift masks are discussed. It was found that 140 nm contact holes with at least 0.5 micrometer depth of focus could be obtained. Cross sections and process windows are shown.

Predicting and reducing substrate induced focus error

The ever shrinking lithography process window requires us to maximize our process window and minimize tool-induced process variation, and also to quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We quantify these effects and their interactions, and present efforts to reduce their harm to the imaging process. We also present our effort to predict design-induced focus error hot spots at the edge of our process window. The collaborative effort is geared towards enabling a constructive discussion with our design team, thus allowing us to prevent or mitigate focus error hot spots upstream of the imaging process.