Ting-Chia Huang

Accelerated SLID bonding using thin multi-layer copper-solder stack for fine-pitch interconnections

Emerging 2.5D and 3D package-integration technologies for mobile and high-performance applications are primarily limited by advances in ultra-short and fine-pitch off-chip interconnections. A range of technologies are being pursued to advance interconnections, most notably with direct Cu-Cu interconnections or Cu pillars with solder caps. While manufacturability is still a major concern for the Cu-Cu interconnections technologies, the copper-solder approaches face limitations due to solder-bridging at fine-pitch, electromigration, and reliability issues. Thus, novel low-temperature, low-pressure, high-throughput, cost-effective and manufacturable technologies are needed to enable interconnections with pitches finer than 15 microns. This paper focuses on an innovative multi-layered copper-solder stack approach to achieve fine-pitch off-chip interconnections with no residual solders after assembly. Interconnections using this new technology enable higher current-handling because of the stable intermetallics, high-throughput assembly, and high yield even at low stand-off heights. The elimination of solder-intermetallic (IMC) interfaces is also expected to enhance the joint strength. This paper describes the design, fabrication, assembly and characterization of such stacked copper-solder interconnections. A detailed study of the effect of bonding parameters such as temperature and time on the rate of formation of stable Cu-IMC-Cu structures is presented. Test-vehicles were designed and fabricated as the first demonstration of this technology.

Interconnection materials, processes and tools for fine-pitch panel assembly of ultra-thin glass substrates

The needs for higher speed and bandwidth at low power for portable and high-performance applications has been driving recent innovations in packaging technologies with new substrate platforms with finer lithographic capability and dimensional stability, such as ultra-thin glass, to enable off-chip interconnections pitch scaling, down to 30μm. Copper pillar flip-chip thermocompression bonding (TCB) has subsequently become a pervasive technology in the past decade, and is now considered as the next interconnection and assembly node for smart mobile and high-performance systems. However, additional innovations are needed to achieve high-throughput thermocompression bonding on fragile and thin glass, with short cycle times and process conditions within HVM (high-volume manufacturing) tool capability. These include material advances in surface finishes and pre-applied underfill materials with built-in flux, along with a unique co-development strategy to provide high-speed solutions with optimized TCB profiles that consider the dynamic thermal behavior of high-density glass substrates, underfill curing kinetics, as well as tool compatibility. These innovations are the key focus of this paper. Finite element heat transfer and thermomechanical modeling were carried out to emulate assembly processes and compare the behavior of glass substrates to that of current technologies. Residual stresses created during the cool-down phase were extracted to help define process windows for stress management in interconnections, by fine control of intermetallics (IMC) formation. Emerging surface finish chemistries compatible with high-density wiring with sub-10μm spacings, such as OSP or EPAG (electroless Pd, autocatalytic Au) finish, were also evaluated for their effect on the formed IMC systems. A new set of no-flow snap-cure underfill materials with high thermal stability, beyond existing conductive films or pastes, was developed in synergy with tools and processes for compatibility with advanced substrate technologies. Model predictions were validated with assembly trials on ultra-thin glass and organic substrates with 100μm thin cores. Design guidelines for bonding tools, materials and processes were finally derived, for high-speed thermocompression bonding, customized to the performance, reliability and cost needs of next-generation mobile and high-performance systems.

Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost

Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.

Design, Demonstration and Characterization of Ultra-Thin Low-Warpage Glass BGA Packages for Smart Mobile Application Processor

This paper presents the design, fabrication, assembly, and characterization of a fully-integrated single-chip glass BGA package at 40/80 μm off-chip I/O pitch with multilayered wiring and through-package-vias (TPVs) at 160 μm pitch. The designed test vehicle emulates an application processor package for smart mobile applications, and enables for the first time measurements of DC signal transmission from the die to the board, through the package, at this density and pitch. A daisy chain test die, 10 mm × 10 mm in size, was designed to emulate a logic processor chip comprising 5448 I/Os distributed in four peripheral rows at 40/80 μm pitch and a central area array at 150 μm pitch. The test dies were fabricated and bumped with standard Cu pillars by ASE. The glass package design included four routing layers, with blind vias (BVs) and TPVs both at 150 μm pitch, to connect 176 I/Os to the board, with BGAs at 400μm pitch. Independent multi-level test structures were added for evaluation of TPV and BV yield during fabrication, as well as partial chip-and board-level interconnection yield and reliability. The TPVs in glass were achieved by a via-first process with a high-throughput plasma etching and primer drilling method. Semi-additive processes (SAP), combined with wet chemical surface treatment methods were applied for patterning of the multi-layer wiring with a minimum of 20 μm Cu trace width at 40 μm pitch. A fan-in fan-out finger design was implemented on the top layer for bump-on-trace chip-level interconnections. Chip assembly on glass panels was carried out by high-speed thermocompression bonding with non-conductive paste (TC-NCP) with the new high-performance APAMA chip-to-substrate (C2S) bonder by Kulicke and Soffa. Yield of each process step was evaluated through fabrication and assembly by DC electrical characterization of TPV, BV and chip-level interconnection daisy chains. Die-to-substrate interconnections were characterized, demonstrating signal transmission through the fully-integrated glass package for the first time at this I/O pitch.

Modeling, design and demonstration of ultra-short and ultra-fine pitch metastable Cu-Sn interconnections with high-throughput SLID assembly

Advances in high-performance package with high I/O densities, and power modules with escalating current needs are driving the need for a new class of interconnection technologies, with thermal stability, current-carrying capability and pitch scalability beyond that of traditional solders. Solid-liquid interdiffusion (SLID or SoLID) or transient liquid phase (TLP) bonding systems, in which the bonding layer is fully converted to intermetallics, are highly sought after to extend the applicability of solders to pitches below 30μm, and for die-attachment in high-temperature high-power systems. This paper introduces an innovative SLID concept, consisting of isolating a metastable intermetallic phase between barrier layers for a faster conversion to metastable composition than that in traditional SLID. The Cu-Sn system was used for this demonstration with a designed transition to metastable Cu6Sn5 instead of the stable Cu3Sn phase, usually targeted. The novel interconnection structure enables assembly within seconds and improved thermomechanical reliability, with all the benefits of SLID bonding such as outstanding thermal stability over 10x reflow and enhanced power handling capability with a current density of 105 A/cm2. The paper first describes the design and fabrication of the interconnection structure, including the barrier and bonding layers based on diffusion and thermomechanical modeling. Ultra-fast assembly by low-pressure thermocompression bonding was demonstrated on die-attach joints and interconnections at 100μm pitch, followed by extensive reliability characterization, including thermal stability evaluation, electromigration test, and die-shear test. The designed interconnections successfully passed JEDEC standards, qualifying this novel interconnection technology for high-temperature, high-power operations at fine-pitch.

Demonstration of Enhanced System-Level Reliability of Ultra-Thin BGA Packages with Circumferential Polymer Collars and Doped Solder Alloys

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100μm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200μm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250μm BGA at 400μm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moiré warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.

Scaling Cu Pillars to 20um Pitch and Below: Critical Role of Surface Finish and Barrier Layers

High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder volume is reduced All-intermetallic interconnections formed by solid-liquid interdiffusion (SLID) bonding have been concurrently explored to extend solders to finer pitches and improve their performance, but face their own set of manufacturability and reliability challenges that have, so far, limited their use to 3D-ICs. This research comprehensively addresses these challenges with innovative interconnection designs and advances in surface finish metallurgies, which allow for precisely controlled and unique interfacial reactions. A two-fold approach is pursued to: 1) extend scalability of conventional Cu pillars by replacing standard ENEPIG with ultra-thin electroless Pd autocatalytic Au (EPAG) surface finish, and, for further pitch scaling and enhanced electrical and thermal performances, 2) enable void-free, manufacturable all-intermetallic joints solely composed of the metastable Cu6Sn5 phase by introduction of diffusion barrier layers. This paper presents the design, demonstration and characterization of such high-performance solder-based interconnections at 20um pitch, highlighting the strategic role of surface finish and diffusion barrier layers for potential further pitch scaling.

Thermocompression Bonding Process Design and Optimization for Warpage Mitigation of Ultra-Thin Low-CTE Package Assemblies

Increasing needs for functionality, performance and system miniaturization in fine-pitch consumer applications have been driving a new class of ultra-thin interposers and packages with larger body sizes, aggravating warpage. These trends gave rise to serious concerns for assembly yield and reliability, especially at board level. The recent adoption of substrate technologies with silicon-matching coefficient of thermal expansion (CTE) reinforces these concerns by introducing a large CTE mismatch between package and organic board. Warpage control and mitigation in assembly has, therefore, become critical in enabling reliable SMT interconnection of ultra-thin, large, low-CTE BGA packages to the board. Copper pillar thermocompression bonding (TCB) has emerged as a key assembly technology to improve die assembly yield at pitches below 80μm and large die sizes. In TCB, heat is applied from the die side only while the substrate is maintained at a low stage temperature, as opposed to isothermal heating in mass reflow. The temperature gradient in the package can, therefore, be finely tuned providing control over the warpage behavior. This paper investigates TCB-induced warpage and its dependence on the bonding thermal profiles in a single-chip, 200μm-thick, low-CTE organic package at 50μm pitch and 17mm x 17mm body size. Warpage trends as a function of the stage temperature were first predicted with a simple coupled thermal-structural finite-element model, then experimentally validated by Shadow-Moiré measurements of assemblies built with varying stage temperatures from 70°C to 150°C. Interactions with the thermocompression tool, in particular the effect of vacuum-coupling of the substrate to the stage, were considered and investigated. Guidelines for design of TCB profiles for warpage minimization were finally derived with considerations of assembly throughput to improve board-level SMT yield and system-level reliability.