Satomi Kawamoto

The effect of filler on the solder connection for no-flow underfill

Miniaturizing and lightening of flip chip packages are now being evaluated because high performance and high density of semiconductors are rapidly advancing. Furthermore, various assembly processes are evaluated because conventional assembly process has its limitation for narrow gap and fine pitch. One of these processes is no-flow underfill (NUF) process. Fluxing NUF is applied on the substrate prior to bonding of the IC with local reflow by flip chip bonder (FCB). High density/narrow gap/fine pitch are possible in the area around the chip because NUF is applied on the substrate before bonding IC. In addition, bump connection and material cure can be done at the same time on NUF process, and also the process can be simplified. Underfill is generally blended with inorganic filler such as silica filler due to its high reliability. It is not an exception on NUF either. Blending filler is indispensable. But as for NUF, defect of solder connection by filler penetration into solder is considered. This paper presents the evaluation of the filler effect on the solder connection for NUF. At first solder connection was confirmed using NUF with/without silica filler. Even if it contained the filler, we found out that good connection was obtained. After grinding the surface, we observed the connection between the solder and the pad. Filler existed inside the solder connection. Furthermore when the amount of filler loading is increased into NUF, the amount of remaining filler at the connection is increased, too. Next we focused on the remained filler on the connection between the solder and the electrode; we confirmed the effect of interface strength by filler left on the contact. As the amount of remained filler was increased, there was a tendency that shear strength of the connection was degraded. We found that controlling filler is important for getting good connection and high shear strength of connection. So we evaluated the effect of shear strength of connection and connectivity by filler size and surface treatment of filler. Finally, the relation between the quantity of remained filler and reliability of connection was evaluated by reliability test. As a result, condition of including filler with NUF was optimized

Effect of NCF design for the assembly of Flip Chip and reliability

Recently, design of Flip Chip (FC) Package is changing with the higher density of the Package. Conventional process with Capillary Underfill (CUF) is not applicable to PKGs such as 3D and chip stacked types. To solve these problems, other processes are being developed in which an encapsulant is applied on a substrate before bonding IC. One of those is the process with Non Conductive Film (NCF). In this process, after NCF is applied, IC is bonded. Interconnection and NCF cure are done at the same time. Therefore, the design of NCF has great influences to FC assembly in terms of void, interconnectability and reliability. Thus, in this paper, we are mainly discussing the optimization of NCF design. At first, we looked at the aspect of voids. One of the causes of voids is captured air which generates when an IC connects to NCF. This relates to the flow of resin. Regarding this flow, we looked into what encapsulants behavior is effective in controlling voids by measuring temperature and viscosity with a rheometer. As a result, we could decrease the voids by optimizing the minimum melting viscosity. As another type, the void from volatilization gas may occur from an organic substrate. We looked at the quantity of substrate using TG-DTA, and found that it decreased by 0.4% till the temperature reached 260°C. Then we found that the higher minimum melting viscosity is, the more effectively this type of voids can be controlled. Moreover we tried to optimize minimum melting viscosity, curability and flux-ability for good interconnection. Regarding the minimum melting viscosity, when it is too high, the connection will be poor. Regarding curability, when cure speed is too high, solder melting will be blocked. We also attempted to optimize flux activity, and found that gelling time, minimum melting viscosity and oxidation-reduction power need to be controlled. Based on these approaches, it became possible to design the NCF which is voidless, has good connection, and can pass the reliability test (JEDECL3, TC1000cyc).

Interconnection materials, processes and tools for fine-pitch panel assembly of ultra-thin glass substrates

The needs for higher speed and bandwidth at low power for portable and high-performance applications has been driving recent innovations in packaging technologies with new substrate platforms with finer lithographic capability and dimensional stability, such as ultra-thin glass, to enable off-chip interconnections pitch scaling, down to 30μm. Copper pillar flip-chip thermocompression bonding (TCB) has subsequently become a pervasive technology in the past decade, and is now considered as the next interconnection and assembly node for smart mobile and high-performance systems. However, additional innovations are needed to achieve high-throughput thermocompression bonding on fragile and thin glass, with short cycle times and process conditions within HVM (high-volume manufacturing) tool capability. These include material advances in surface finishes and pre-applied underfill materials with built-in flux, along with a unique co-development strategy to provide high-speed solutions with optimized TCB profiles that consider the dynamic thermal behavior of high-density glass substrates, underfill curing kinetics, as well as tool compatibility. These innovations are the key focus of this paper. Finite element heat transfer and thermomechanical modeling were carried out to emulate assembly processes and compare the behavior of glass substrates to that of current technologies. Residual stresses created during the cool-down phase were extracted to help define process windows for stress management in interconnections, by fine control of intermetallics (IMC) formation. Emerging surface finish chemistries compatible with high-density wiring with sub-10μm spacings, such as OSP or EPAG (electroless Pd, autocatalytic Au) finish, were also evaluated for their effect on the formed IMC systems. A new set of no-flow snap-cure underfill materials with high thermal stability, beyond existing conductive films or pastes, was developed in synergy with tools and processes for compatibility with advanced substrate technologies. Model predictions were validated with assembly trials on ultra-thin glass and organic substrates with 100μm thin cores. Design guidelines for bonding tools, materials and processes were finally derived, for high-speed thermocompression bonding, customized to the performance, reliability and cost needs of next-generation mobile and high-performance systems.

Design, Demonstration and Characterization of Ultra-Thin Low-Warpage Glass BGA Packages for Smart Mobile Application Processor

This paper presents the design, fabrication, assembly, and characterization of a fully-integrated single-chip glass BGA package at 40/80 μm off-chip I/O pitch with multilayered wiring and through-package-vias (TPVs) at 160 μm pitch. The designed test vehicle emulates an application processor package for smart mobile applications, and enables for the first time measurements of DC signal transmission from the die to the board, through the package, at this density and pitch. A daisy chain test die, 10 mm × 10 mm in size, was designed to emulate a logic processor chip comprising 5448 I/Os distributed in four peripheral rows at 40/80 μm pitch and a central area array at 150 μm pitch. The test dies were fabricated and bumped with standard Cu pillars by ASE. The glass package design included four routing layers, with blind vias (BVs) and TPVs both at 150 μm pitch, to connect 176 I/Os to the board, with BGAs at 400μm pitch. Independent multi-level test structures were added for evaluation of TPV and BV yield during fabrication, as well as partial chip-and board-level interconnection yield and reliability. The TPVs in glass were achieved by a via-first process with a high-throughput plasma etching and primer drilling method. Semi-additive processes (SAP), combined with wet chemical surface treatment methods were applied for patterning of the multi-layer wiring with a minimum of 20 μm Cu trace width at 40 μm pitch. A fan-in fan-out finger design was implemented on the top layer for bump-on-trace chip-level interconnections. Chip assembly on glass panels was carried out by high-speed thermocompression bonding with non-conductive paste (TC-NCP) with the new high-performance APAMA chip-to-substrate (C2S) bonder by Kulicke and Soffa. Yield of each process step was evaluated through fabrication and assembly by DC electrical characterization of TPV, BV and chip-level interconnection daisy chains. Die-to-substrate interconnections were characterized, demonstrating signal transmission through the fully-integrated glass package for the first time at this I/O pitch.

Modeling, design and demonstration of ultra-short and ultra-fine pitch metastable Cu-Sn interconnections with high-throughput SLID assembly

Advances in high-performance package with high I/O densities, and power modules with escalating current needs are driving the need for a new class of interconnection technologies, with thermal stability, current-carrying capability and pitch scalability beyond that of traditional solders. Solid-liquid interdiffusion (SLID or SoLID) or transient liquid phase (TLP) bonding systems, in which the bonding layer is fully converted to intermetallics, are highly sought after to extend the applicability of solders to pitches below 30μm, and for die-attachment in high-temperature high-power systems. This paper introduces an innovative SLID concept, consisting of isolating a metastable intermetallic phase between barrier layers for a faster conversion to metastable composition than that in traditional SLID. The Cu-Sn system was used for this demonstration with a designed transition to metastable Cu6Sn5 instead of the stable Cu3Sn phase, usually targeted. The novel interconnection structure enables assembly within seconds and improved thermomechanical reliability, with all the benefits of SLID bonding such as outstanding thermal stability over 10x reflow and enhanced power handling capability with a current density of 105 A/cm2. The paper first describes the design and fabrication of the interconnection structure, including the barrier and bonding layers based on diffusion and thermomechanical modeling. Ultra-fast assembly by low-pressure thermocompression bonding was demonstrated on die-attach joints and interconnections at 100μm pitch, followed by extensive reliability characterization, including thermal stability evaluation, electromigration test, and die-shear test. The designed interconnections successfully passed JEDEC standards, qualifying this novel interconnection technology for high-temperature, high-power operations at fine-pitch.

Demonstration of Enhanced System-Level Reliability of Ultra-Thin BGA Packages with Circumferential Polymer Collars and Doped Solder Alloys

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100μm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200μm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250μm BGA at 400μm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moiré warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.

The development of Anisotropic Conductive Paste (ACP) to make solder metal connection

This paper presents the development of the effect of diameter and loading level of solder for connectivity and insulation, in addition we compared to Advanced ACP and conventional ACP, NCP. At first, alloy connection was confirmed using ACP with solder particle. The Chip was torn off after bonding, we confirmed melting solder at the surface of Bump and Pad. Solder alloy layer was confirmed between Bump and Pad by observation of cross-section. As these results, we concluded that the alloy layer could be formed due to the intervention of the solder.

Interfacial Delamanination of Mold Compound in Fan-Out Packages

Emerging fan-out packages require advances in mold compounds, polymer interfaces to metals and silicon, and innovative processing to reach the required high reliability. In this paper, we discuss the fracture energy for mold compound interface to copper and silicon, and use that information for studying interfacial delamination propagation of mold compound. We have examined mold compound delamination from silicon die as well as redistribution layer in a fan-out package, and compared the results against a lead-frame package as well as a plastic ball grid array package of similar dimensions.

Thermocompression Bonding Process Design and Optimization for Warpage Mitigation of Ultra-Thin Low-CTE Package Assemblies

Increasing needs for functionality, performance and system miniaturization in fine-pitch consumer applications have been driving a new class of ultra-thin interposers and packages with larger body sizes, aggravating warpage. These trends gave rise to serious concerns for assembly yield and reliability, especially at board level. The recent adoption of substrate technologies with silicon-matching coefficient of thermal expansion (CTE) reinforces these concerns by introducing a large CTE mismatch between package and organic board. Warpage control and mitigation in assembly has, therefore, become critical in enabling reliable SMT interconnection of ultra-thin, large, low-CTE BGA packages to the board. Copper pillar thermocompression bonding (TCB) has emerged as a key assembly technology to improve die assembly yield at pitches below 80μm and large die sizes. In TCB, heat is applied from the die side only while the substrate is maintained at a low stage temperature, as opposed to isothermal heating in mass reflow. The temperature gradient in the package can, therefore, be finely tuned providing control over the warpage behavior. This paper investigates TCB-induced warpage and its dependence on the bonding thermal profiles in a single-chip, 200μm-thick, low-CTE organic package at 50μm pitch and 17mm x 17mm body size. Warpage trends as a function of the stage temperature were first predicted with a simple coupled thermal-structural finite-element model, then experimentally validated by Shadow-Moiré measurements of assemblies built with varying stage temperatures from 70°C to 150°C. Interactions with the thermocompression tool, in particular the effect of vacuum-coupling of the substrate to the stage, were considered and investigated. Guidelines for design of TCB profiles for warpage minimization were finally derived with considerations of assembly throughput to improve board-level SMT yield and system-level reliability.

Fundamental Research of No-Flow UF for Low Stress Flip-Chip Package

Recently, most of semiconductor companies are developing high density packages using lead free solder and low-k layer. The melting temperature of lead free solder is higher than the eutectic solder. Therefore, the reflow profile for lead free solder is higher approximately 30 degrees C than the conventional profile. When a high temperature profile is used, the organic substrate is expanded and the package stress becomes higher. Furthermore, bump cracking by the package stress is concerned, because lead free solder is very fragile. In addition, it is easy to destroy the low-k layer by the package stress such as the packages warpage. Thus the stress control is necessary for the assembly process of high density packages using lead free solder and low-k layer. It is effective to use no-flow underfill (NUF) with local reflow process using a flip chip bonder (FCB). This process can realize an assembly with lower stress compared with capillary flow underfill (CUF) reflow process, because the organic substrate should not be exposed to a high temperature and is controlled not to expand much. NUF characteristics for local reflow process are investigated. At first, NUF curability and the influence of flux-ability for the solder connection were evaluated using NUF which was based on the epoxy resin and different kinds of hardeners. It was confirmed that solder connection was affected by NUF curability and the flux-ability were influenced by the hardener type. Then filler loading level was optimized to reinforce the solder joint. We improved the mismatch between IC chip and substrate in the C.T.E (coefficient of thermal expansion). NUF of various filler contents were evaluated under reliability tests such as moisture reflow test, temperature cycle test, and high temperature/high humidity test. Finally the package stress with a low stress NUF was evaluated by shadow moire technique. As a result, it was confirmed that the package by local reflow process had a lower stress than the package by conventional process