Motomu Ukita

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

A single bitline cross-point cell activation (SCPA) architecture that reduces active power consumption and reduces the chip size of high-density SRAMs (static random access memories) is presented. The architecture enables the smallest column current possible without increasing the block division of the cell array. Since the decoder area is reduced due to less block division, the memory core can be smaller than with a conventional divided word line (DWL) structure. In the SCPA, the total active current is 15.9 mA, while in the conventional architecture it is 26.1 mA. In the SCPA, the memory cell size is equal to that in the conventional architecture; however, the number of local decoders is reduced from 64 to 8. Moreover, the number of GND lines is reduced because of a much smaller column current in SCPA. As a result, the area of the memory core is reduced by 10% in a 16-Mb SRAM. >

A 21-mW 4-Mb CMOS SRAM for battery operation

The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 mu A. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6- mu m process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined. >

Variable bit organization as a new test function for standard memories

A variable bit-organization function that enables the RAM to be used in plural bit organizations is proposed. This function reduces the test time for many kinds of test patterns and data patterns. Consequently, a short-time, accurate, and severe test is realized. This test-time reduction function is important in a high-speed memory such as SRAM because it preserves the same access time for the different organizations. Using the output driver transistor as the input protection circuit, a low and uniform input/output pin capacitance of 3.5 pF and a high electrostatic discharge (ESD) immunity have also been realized. This function has been successfully implemented in a 1-Mb SRAM configurable for both 1-M-word*1-b and 256K-word*4-b organizations without any practical drawbacks. >