Tonia G. Morris

Object-based selection within an analog VLSI visual attention system

An object-based analog very large-scale integration (VLSI) model of selective attentional processing has been implemented using a standard 2.0-/spl mu/m CMOS process. This chip extends previous work on modeling a saliency-map-based selection and scanning mechanism to incorporate the ability to group pixels into objects. This grouping, or segmentation, couples the circuitry of the objects pixels to act as a single, larger pixel. The grouping of pixels is dynamic, driven solely by the segmentation criterion at the input. In this demonstration circuit, image intensity has been chosen for the input saliency map and the segmentation is based on spatial low-pass filtering followed by an intensity threshold. We present experimental results from a one-dimensional implementation of the object-based analog VLSI selective-attention system.

8 x 8 array of thin-film photodetectors vertically electrically interconnected to silicon circuitry

This paper reports the integration of an 8/spl times/8 array of thin-film GaAs-AlGaAs photodetectors onto a silicon-oscillator array circuit for massively parallel-image processing applications. Each detector was electrically connected to the oscillator below it using vertical electrical interconnections. Both sides of the thin-film devices were metallized for electrical contact, which minimized the interconnection density on the silicon circuit, thereby maximizing the available signal processing area. The yield of this integrated array and associated circuit was 100%, with the majority of pixels demonstrating a dynamic range of 50 dB.<<ETX>>

Analog VLSI Excitatory Feedback Circuits for AttentionalShifts and Tracking

In this paper we present analog very large-scale integrated(VLSI) circuits that perform the selection process for attentivevisual processing. These circuits use excitatory feedback ina winner-take-all computation to produce a hysteresis in theselection from one location to the next. We present several alternativeforms of excitation that can be used to enhance surrounding regionsof the presently attended location. Each form of excitation isdiscussed and experimental results from a one-dimensional arrayare presented. We also demonstrate the performance of these circuitswithin a system that receives optical inputs and outputs a singlevoltage that encodes the position of attention. The system demonstratesthe potential use of these excitatory feedback circuits for electronictracking of a stimulus within a noisy environment.

Analog VLSI circuits for primitive sensory attention

Circuitry that performs primitive attention tasks is presented. With the addition of feedback to a winner-take-all circuit we are able to mediate the selection of a single location within a sensory array through the use of hysteresis.<<ETX>>

Analog VLSI circuits for covert attentional shifts

In this paper we present analog very large-scale integrated (aVLSI) circuits that facilitate the selection process for initiating and mediating attentive visual processing. We demonstrate the performance of these circuits within a system that implements covert attentional shifts based on an input array that represents saliency across the visual field. The selection process, which enables the transition from preattentive to attentive processing, uses knowledge of previous selections and appropriate duration of selections to perform its task. The circuitry uses local feedback to create a hysteretic effect in the switching from one location of attention to the next. We also include an inhibition-of-return mechanism to facilitate shifting the location of attention even when the input array remains constant. We present test data from a one-dimensional version of the system.

A two-dimensional, object-based analog VLSI visual attention system

A two-dimensional object-based analog VLSI model of selective attentional processing has been implemented using a standard 1.2 /spl mu/m CMOS process. This chip extends previous work modeling object-based selection and scanning by incorporating the circuity and architectural changes necessary for two-dimensional focal plane processing. To balance the need for closely spaced large photodetectors with the space requirements of complex in-pixel processing, the chip implements a multiresolution architecture. The system has he ability to group pixels into objects; this grouping is dynamic, driven solely by the segmentation criterion at the input. In the demonstration system, image intensity has been chosen for the input saliency map and the segmentation is based on spatial lowpass filtering followed by an intensity threshold. We present experimental results.

Analog VLSI arrays for morphological image processing

A two-dimensional analog VLSI array that performs basic morphological image processing operations is presented. The system uses a smart pixel approach that facilitates the parallel computation of continuous real-time outputs. Photodetectors within the array of smart pixels also allow for parallel optical inputs. The processing is performed by current-mode circuitry implemented with CMOS technology. The signal values are encoded as analog current values. The processing array uses local communication to perform the morphological operation known as dilation, and outputs the difference between the original input image and the dilation image to detect edges. The system was fabricated using a standard 2.0 /spl mu/m digital CMOS process. Example output data of the fabricated circuitry are presented.<<ETX>>

A Smart-Scanning Analog VLSI Visual-Attention System

We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.

Analog VLSI circuits for manufacturing inspection

We present three types of analog VLSI circuits that can be used in manufacturing inspection systems. The first set of circuits performs an adaptive threshold of an input image. The second circuit uses morphological operations with programmable structuring elements to detect oriented edges. Both of these circuits can be used as high speed preprocessors for visual inspection of manufacturing processes. The third circuit performs a computation necessary for selective attention in visual processing. This circuit is a component of a larger system that will facilitate a serial/parallel processing scheme in order to increase the speed of processing in machine vision tasks. Ail circuits presented use focal-plane processing to achieve their massively parallel architectures. For each design, the processing pixels contain vertical bipolar phototransistors to accommodate parallel optical inputs. All circuits have been fabricated using a standard 2.0 /spl mu/m digital CMOS process. Data for each of these circuits is presented.

An analog VLSI focal-plane processing array that performs object-based attentive selection

We have implemented a CMOS focal-plane processing array that performs a selection algorithm based on the intensity profile of the input image. Objects within the image are segmented by normalization, filtering, and thresholding. The selection processing circuits use aggregate information from each object in order to select the most important object within the visual field. All pixel processing is implemented with analog subthreshold circuits. The system includes a multiresolution array of pixels that comprise a 50/spl times/48 array of photoreceptors and a 25/spl times/24 array of object-based selection processing circuits. On-chip scanners are used to simultaneously display the input and output arrays directly on a multisync monitor. Position-encoding circuitry is also included on the chip in order to output two analog values that indicate the selected position on the array. The system was fabricated in a standard 1.2 /spl mu/m digital CMOS process. We present experimental results.