Toshiharu Katayama

Ultrathin Silicon Nitride Films Fabricated by Single‐Wafer Processing Using an SiH2Cl2 ‐ NH 3 ‐ H 2 System and In Situ H 2 Cleaning

We demonstrated the formation technique of highly reliable ultrathin oxidized silicon nitride film (34 A in oxide equivalent thickness) on three-dimensional cylindrical stacked capacitor cells. In situ H 2 cleaning and low-pressure chemical vapor deposition of silicon nitride using SiH 2 Cl 2 and NH 3 gases were successively carried out in a reactor, which can accommodate an 8 in. silicon wafer. The conduction current through the film was suppressed and the time-to-breakdown was substantially improved by the complete elimination of the bottom oxide. The intrinsic lifetime of the cylindrical stacked capacitors, which was comparable to that of the conventional stacked capacitors, was estimated to be long enough for use in 256 Mbit dynamic random access memory (DRAM). This result has revealed that the present single-wafer process is very effective and practical for the three-dimensional capacitor formation of the next generation DRAMs.

Accurate Thickness Determination of Both Thin SiO2 on Si and Thin Si on SiO2 by Angle-Resolved X-Ray Photoelectron Spectroscopy

Thicknesses of both ultrathin silicon oxide on silicon substrate and ultrathin silicon on silicon oxide are accurately determined by angle-resolved X-ray photoelectron spectroscopy (AR-XPS). The effective attenuation lengths of Si 2p photoelectrons in silicon oxide, λO, and silicon substrate, λS, are accurately determined by considering the photoelectron yields in both materials, which were obtained experimentally from the damping of intensities of the plasmon-loss peaks therein. Photoelectron yields for silicon oxide and silicon substrate are YO = 0.91 and YS = 0.74, respectively, and consequently the relationship between λO and λS is λO=1.4 λS. The value of λS is accurately determined from the silicon-on-insulator (SOI) sample with a thickness of 5 nm to be λS = 2.3 nm and the value of λO is subsequently determined to be 3.2 nm. Finally, the value of λO is confirmed by comparing the oxide thicknesses of SiO2 on Si(100) systems determined by AR-XPS with those determined by ellipsometry.

Analysis of Junction Leakage Current Failure of Nickel Silicide Abnormal Growth Using Advanced Transmission Electron Microscopy

This is the first paper to reveal the formation mechanism of the abnormal growth of nickel silicide that causes leakage-current failure in complementary metal-oxide- semiconductor (CMOS) devices by using advanced transmission electron microscope (TEM) techniques: electron tomography and spatially-resolved electron energy-loss spectroscopy (EELS). We reveal that the abnormal growth of Ni silicide results in a single crystal of NiSi2 and that it grows toward Si <;110> directions along (111) planes with the Ni diffusion through the silicon interstitial sites. In addition, we confirm that the abnormal growth is related to crystal microstructure and crystal defects. These detailed analyses are essential to understand the formation mechanism of abnormal growths of Ni silicide.

Three-Dimensional Visualization Technique for Crystal Defects in High Performance p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Embedded SiGe Source/Drain

We have performed a detailed analysis of crystal defects in high-performance p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with embedded SiGe source/drain (S/D), using low-angle annular dark field (ADF) scanning transmission electron microscopy (STEM) and electron tomography. We achieved successful results in three-dimensional visualization of crystal defects for the first time. Consequently, we have discussed about the three-dimensional physical geometric relationship between crystal defects and device architecture. This approach is sure to contribute to the development of advanced complementary metal–oxide–semiconductor (CMOS) devices using strained silicon technology.

Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

The lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor is one of the key elements of high-power devices. It is difficult to evaluate the degradation of an LDMOS at the required temperature range, because the self-heating effect of an LDMOS is too large for conventional evaluation in DC. In this paper, we report on the hot carrier degradation of an LDMOS under high-power operation, by investigating the LDMOS deterioration in the case that both the device structure and junction temperature (Tj) are different. The Tj of an LDMOS is controlled by operating the gate voltage (Vg) in pulse mode. Controlling Tj by operating Vg in pulse mode, the Tj dependence of hot carrier degradation under high-power operation can be evaluated widely and quantitatively. The threshold voltage (Vth) shift is observed according to the bias temperature mode irrespective of the device structure. On the other hand, the shift of drain current is affected by the length of the accumulation region under the gate electrode, and a relatively small increase in drain current (Ids) shift is observed with decreasing Tj. These phenomena are clarified from the results of charge pumping measurement and simulation.

Guest Editorial Special Section on the 2016 International Symposium on Semiconductor Manufacturing

Since its start in 1992 in Japan, the International Symposium on Semiconductor Manufacturing (ISSM) has provided unique opportunities to share the best practices of semiconductor manufacturing technologies for professionals worldwide. At the symposium, professionals assemble to discuss the technologies developed to meet worldwide requirements for advanced semiconductor manufacturing. It is crucial to re-examine semiconductor manufacturing in terms of fundamental principles to improve the performance of devices. In addition, manufacturing technologies that preserve the Earth’s environment will require new concepts and stronger collaborative efforts to find precompetitive solutions to the challenges posed.