Toshihiko Himeno

A new technique for measuring threshold voltage distribution in flash EEPROM devices

A new, simple test circuit for evaluating the reliability of flash EEPROM devices is described. It measures threshold voltage (V/sub th/) distributions of a large number of cell transistors with easy static operation similar to I-V curve measurement. Moreover, each cell transistor in a large array is selectable to measure static characteristics. This circuit makes it possible to measure the V/sub th/ distribution even in the negative region after erase operation for a NAND-type EEPROM.

A 120-mm/sup 2/ 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-/spl mu/s random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-/spl mu/m single-metal CMOS process resulting in a die size of 120 mm/sup 2/ and an effective cell size of 1.1 /spl mu/m/sup 2/.

A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology

Higher density flash memories for mass storage are attractive for application in the audio-video field, for example, in digital cameras and for voice recording. A 100 MB Flash records one hour CD-quality music. Improvements in video compression techniques are expected to realize gigabyte flash, enabling movies on silicon in the near future; a development that is expected to lead to rapidly rising demand for high-density flash. Both the low bit cost due to the small cell size and the high program and read performance are important factors for the high density flash. A NAND flash has potential advantages in those respects. Shallow trench isolation (STI) shrinks bit line pitch to 73% of that in the case of conventional LOCOS isolation, enabling 0.29 um/sup 2/ cell 0.25 /spl mu/m design rules. The 129.76 mm/sup 2/ chip is made possible by using NAND type memory cell and STI.

A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective cell size including the select transistors is 0.077 /spl mu/m/sup 2/. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm/sup 2/ and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.

A source-line programming scheme for low voltage operation NAND flash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 /spl mu/s/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme.

A 113mm2 32Gb 3b/cell NAND flash memory

NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND Flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low cost per bit, technical improvement in feature-size scaling [1], multi-bit per cell [2,3] and area reduction are essential.

A 120 mm/sup 2/ 64 Mb NAND flash memory achieving 180 ns/byte effective program speed

Rapidly increasing solid-state mass-storage application areas are requiring low cost, high density flash memories with higher read and program throughputs. This paper describes a 3.3 V-only 64 Mb NAND flash memory fabricated using a 0.4 /spl mu/m single-metal CMOS technology. The read throughput of 40 MB/s is achieved by improving the random access time and by introducing a full-chip burst read. A typical program throughput of 5 MB/s corresponding to 180 ns/byte is achieved by using a narrow incremental step pulse programming (NISPP) technique. A staggered row decoder scheme relaxes layout limitations and improves the random access time.

A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit

A 7.07 mm2 synthesizable streaming processing unit (SPU) is fabricated in a 65 nm CMOS technology with 8 level copper layers. It is migrated from its original custom design to a synthesizable design to get higher design portability. New features are a new floor plan, height optimized standard cell library, local clock generator cloning and adaptive wire width control. Its logic area is 30% smaller than the full custom designed SPU in the same process generation. Correct functional operation is realized in 4 GHz at 1.4 V.

Quick address detection of anomalous memory cells in a flash memory test structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test.

A quick address detection of an anomalous memory cell for flash EEPROM

A simple technique for quickly detecting an address of an anomalous memory cell for flash EEPROM devices is described. A proposed Multi-Address Selection Scheme (MASS) can drastically reduce measurement cycles for searching an address of an anomalous memory cell which has an abnormally high or low threshold voltage. A systematic evaluation for the reliability of flash EEPROM has been realized by this quick address detection technology.