Tsuneaki Fuse

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

SOI CMOS with gate-body connection (DTMOS) and body bias controlled SOI pass-gate logic (BCSOI pass-gate) take advantage of individually isolated SOI device active area and reduce threshold voltage by controlling each device body bias. Hence, they enjoy higher speed than circuits based on fixed low threshold voltage. The direct body bias control used in previous work suffers from leakage current at supply voltage higher than 0.8V due to drain-body junction leakage. A practical circuit technology that offers the highest speed, lowest operation voltage and stable operation under wide supply voltage demonstrates performance with an ALU macro using this technology.

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

A 5-V 4M-word*4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7- mu m triple-tub CMOS technology is discussed. The RAM utilizes a recently developed STT (stacked trench capacitor) cell which achieved 37 fF in a small cell size of 1.7*3.6 mu m/sup 2/. The STD (sidewall transistor with double-doped drain) structure is used for PMOS-FETs to realize high-speed operation. To ensure MOSFET reliability, the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. An on-chip interleaved circuit and double-input-buffer scheme is used to realize high-speed serial read/write operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and RAS access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time. >

0.5 V SOI CMOS pass-gate logic

Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.

A new static memory cell based on reverse base current (RBC) effect of bipolar transistor

A novel SRAM (static random access memory) cell, which consists of a bipolar transistor and an MOS transistor, is proposed. The device, which is based on the reverse base current (RBC) effect, has been fabricated by conventional BiCMOS technology, using double poly-Si. A cell size of 8.58 mu m/sup 2/ has been realized in a 1.0- mu m ground rule. The results indicate that the RBC cell can be applied to very-high-density SRAMs, as large as 16 Mb or beyond.<<ETX>>

A new static memory cell based on the reverse base current effect of bipolar transistors

A SRAM cell that consists of a bipolar transistor and an MOS transistor is proposed. The cells principle of operation is based on the reverse base current (RBC) of a bipolar transistor. It has been fabricated by conventional BiCMOS technology, using double-poly Si. A cell size of 8.58 mu m/sup 2/ is realized in a 1.0- mu m ground rule. The mechanism and characteristics of this cell are discussed. >

A 31 GHz f/sub max/ lateral BJT on SOI using self-aligned external base formation technology

A novel device structure and simple process technology for realizing low-power/high-performance SOI lateral BJTs are presented. Low base resistance has been achieved by employing a self-aligned external base formation process. Due to reduced parasitics, the fabricated device exhibited an f/sub max/ of 31 GHz, the highest value for an SOI BJT reported so far.

A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology

Describes a novel power-supply scheme suitable for 0.5V operating LSIs. The system contains the on-chip buck dc-dc converter with over-90% efficiency, 0.5V operating logic, 100MHz operating F/Fs with holding data in the stand-by mode, and the dual-rail level converter. The dc-dc converter TEG, fabricated using 0.35/spl mu/m multi-Vt SOI CMOS process, realized stable recovery characteristics and a final stage efficiency of 92% with 0.5V/10mW output.

A physically based base pushout model for submicrometer BJTs in the presence of velocity overshoot

By using a two-dimensional relaxation time approximation device simulator, base pushout phenomena for submicrometer bipolar junction transistors (BJTs) are analyzed. From the numerical analysis, it was clarified that, under the base pushout condition, the electron velocity exceeds the saturation velocity in most of the epi-collector region. Considering this velocity overshoot effect with two-dimensional carrier behavior, a base pushout model was developed. This model is applicable to the BJT equivalent circuit model. The model utility was verified for a 0.8 mu m emitter-width BIT, and excellent agreement with measured I-V characteristics was obtained over wide injection conditions. Scaling effects on the velocity overshoot are also calculated, based on the constant current scaling. It is shown that the base pushout is suppressed due to the increased velocity overshoot level as the device sizes are scaled down. >

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.

3-D simulation analysis of high performance SOI lateral BJT for RF applications

Summary form only given. In view of the rapid growth of the portable wireless communications market, the development of low-power and low-cost RF device technology is becoming important. The SOI lateral BJT has attracted considerable interest due to its low parasitic capacitance and simplified process. However, in the previous reports (Higaki et al. 1991; Shahidi et al. 1991; Babcock et al, 1996), the maximum f/sub max/ is less than half that of conventional bulk Si counterparts. This is presumably due to the high base-resistance (R/sub b/). In this work, we propose novel and practical SOI lateral BJTs which feature drastically reduced R/sup b/. A maximum operating frequency (f/sub max/) as high as 111 GHz is predicted.