Shigeru Kawanaka

Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling

Steep channel impurity-profiles formed by Si∶C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si∶C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.

Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond

Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-LG nMOSFET. Si:C layers work as the dopant-diffusion-barriers from the boron doped regions. Moreover, retrograde Halo profiles are also realized in this structure. Steep channel profiles at scaled device are confirmed, and the benefits of its profile at LG of 25 nm are discussed.

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

A 31 GHz f/sub max/ lateral BJT on SOI using self-aligned external base formation technology

A novel device structure and simple process technology for realizing low-power/high-performance SOI lateral BJTs are presented. Low base resistance has been achieved by employing a self-aligned external base formation process. Due to reduced parasitics, the fabricated device exhibited an f/sub max/ of 31 GHz, the highest value for an SOI BJT reported so far.

25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)

Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to form steep p-type channel profiles in n-channel MOS field-effect transistors (nMOSFETs) due to extremely low diffusivity of boron and indium in Si:C layers. This structure with low channel impurity improves mobility and suppresses threshold voltage (VTH) variation. Both items are essential for aggressively scaled MOSFETs with a gate length less than 25 nm. We demonstrated well-controlled, high-performance, and low VTH variability nMOSFETs with a Si:C-Si epitaxial channel structure.

In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor

The impacts of source and drain (S/D) doping on device performance in embedded SiGe (e-SiGe) p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) are presented. An in situ boron-doped e-SiGe S/D device exhibits higher drive current than a boron-implanted e-SiGe S/D device owing to its enhanced hole mobility and reduced parasitic resistance. The precise control of the recessed Si shape and the SiGe proximity to the channel is essential for utilizing the intrinsic benefit of an in situ boron-doped e-SiGe S/D. Moreover, it was confirmed that the channel stress induced by e-SiGe S/D increases as MOSFET size decreases. This indicates that the use of in situ boron-doped e-SiGe S/D is a promising technique for 32 nm node pMOSFET.

Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation

Platinum (Pt) incorporation into nickel silicide (NiSi) films improves silicide characteristics such as lower contact resistance RC at silicide/Si interface and higher thermal stability. The impact of Pt incorporation is widely accepted and recognized in research field; however, the role of Pt in NiSi films has not been fully clarified so far. In this paper, the spatial distributions of Pt and dopants (i.e., arsenic and boron) in silicide films are studied at an atomic level analysis using local electrode atom probe. In particular, Pt and dopant distributions were investigated in detail both at silicide/Si interface and at silicide-grain boundary. Silicide-grain size was also analyzed at various Pt concentrations in silicide films, and the relationship between the Pt concentration and physical properties of Ni1-xPtxSi films is pointed out. Finally, for further CMOS device scaling, the benefit of higher concentration of Pt incorporation into Ni1-xPtxSi films is described.

Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling ∼ Atomic level analysis of Pt/B/As distribution within silicide films ∼

Platinum (Pt)-incorporation into nickel silicide films is the promising approach to reduce the contact resistance (RC) at silicide/Si interface. Physical properties of Ni1-xPtxSi films were investigated by using local electrode atom probe (LEAP); The distributions of Pt and dopants (such as As and B) were analyzed both at silicide/Si interface and at silicide grain boundary. The silicide grain-size miniaturization was clearly observed by Pt-incorporation. The impacts of silicide grain size on electrical properties and thermal stability were clarified depending on the Pt concentration. Finally, RC reduction depending on the incorporated-Pt concentration was experimentally shown in both nMOSFETs and pMOSFETs.

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide.

Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 muA/mum at Vdd=1.0 V, Ioff =100 nA/mum at 24 nm gate length, is demonstrated.