Tzu-Yin Chiu

Characteristics of impact-ionization current in the advanced self-aligned polysilicon-emitter bipolar transistor

Using an algorithm to calculate the base current increase due to local thermal effects, the authors show that one can accurately measure the impact ionization current over the full range of collector current. From the measured impact ionization ratio, it was possible to quantitatively describe the characteristics of the space-charge modulation and base push-out effect over a wide range of collector current. Computer simulation results support the measured data. It is also shown that one can use the measured impact ionization ratio to distinguish small collector concentration variations and thickness differences. The characterization was performed for self-aligned polysilicon-emitter transistors in an advanced BiCMOS technology. >

Non-overlapping super self-aligned BiCMOS with 87 ps low power ECL

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. A high-speed frequency divider, a multiplexer, and a demultiplexer operating up to 4.1 GHz, 5.5 Gb/s, and 6.2 Gb/s, respectively, have been fabricated. The results show that NOVA BiCMOS is suitable for Gb/s digital VLSI application.<<ETX>>

A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 /spl mu/m design rules (0.5 /spl mu/m as one nesting tolerance) has achieved f/sub l/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 /spl mu/m/sup 2/) of 23 GHz and 24 GHz at V/sub ce/=3 V, respectively, with BV/sub ceospl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A/sub e/=1/spl times/2 /spl mu/m/sup 2/; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 /spl Aring/, L/sub eff/=0.6 /spl mu/m; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 /spl mu/m; gate L/sub eff/=0.7 /spl mu/m) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW. >

An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts

An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.<<ETX>>

The design and characterization of nonoverlapping super self-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L/sub eff/=1.1 mu m and W/sub n//W/sub p/=10 mu m/10 mu m exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f/sub T/, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated. >

Analytical modeling of oxide breakup effect on base current in n/sup +/-polysilicon emitter bipolar devices

The authors have modeled the base current change with different percentages of broken interface-oxide area (interface void). A pseudo-two-dimensional structure of dual channels of minority-carrier transport at the interface between the polysilicon and the silicon emitter, is constructed in analogy with an electrically equivalent conductance network. Using the conductance network, an analytical expression of base current is easily derived. For typical polysilicon emitter devices of approximately 10-15 AA interface oxide, the experimental results show that the strong dependence of base current on the fraction of interface void can be modeled. The simulation predicts that the base current will be insensitive to the fraction of interface oxide breakup for very thin interface-oxide polysilicon emitter devices. Recent reports on finding a process window between current gain and emitter resistance optimization in a certain range of interface breakup ratios are confirmed by the model. >

Integratable and low base resistance Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors using selective and non-selective rapid thermal epitaxy

We report a new Si/SiGe HBT device structure using selective and non-selective rapid thermal epitaxy. The structure has the potential to simultaneously provide for high level integration and a high Ge fraction strained alloy base which allows high base doping. We used an in-situ As doped polysilicon emitter contact to provide low R/sub E/ (9 to 12 /spl Omega/ for A/sub E/=0.5/spl times/10 /spl mu/m/sup 2/) without the enhanced diffusion effects associated with direct implantation or phosphorous doped poly emitters. In addition, we studied the effects of the extrinsic base implant position on the device I-V characteristics, junction capacitances, and high frequency performance. The collector current increased by over 3 decades as the extrinsic base implant position moved from the single crystal region to an adjacent poly region due to the containment of damage. S-parameter measurements of a 0.5/spl times/10 /spl mu/m/sup 2/ device yielded a cutoff frequency of 54 GHz for V/sub CE/=1.5 V and I/sub C/=14.8 mA.

Direct measurement of base drift field in bipolar transistors

The authors have developed a method to measure an effective base drift field and the base transit-time reduction factor of bipolar transistors, by measuring the excess phase of the base transport factor. This technique relies on measuring small-signal characteristics of the transistor at a low frequency and following the phase of the transconductance at the frequency approaching and exceeding the unit current gain frequency (f/sub T/). With this technique, the authors verify that the effective drift inside the base of Si bipolar transistors decreases with increased base implantation energy and thermal treatment. Such directly measured drift-dependent base transport provides additional insight for optimizing processing used in bipolar technology development.<<ETX>>

Nonoverlapping super self-aligned device structure for high-performance VLSI

The nonoverlapping super self-aligned structure (NOVA) is reported. Because of its nonoverlapping nature, this structure can be applied equally well to bipolar, CMOS, or BiCMOS processes. This structure effectively minimizes parasitic capacitance and resistance for both the MOS and bipolar devices. CMOS and bipolar devices are integrated into a high-performance BiCMOS technology. CMOS and emitter-coupled logic (ECL) ring oscillators with 1.5- mu m lithography are reported to have delays of 128 and 87 ps/stage, respectively.<<ETX>>

A new analytical model and the impact of base charge storage on base potential distribution, emitter current crowding and base resistance

DC emitter crowding effect is modeled analytically for the first time with minority charge storage taken into account. In contrast with previous work that neglected excess carriers, we find that the solution is well behaved without singularity and base voltage pinning. Expressions for base and collector current, large signal and small signal base resistance are also derived. We prove that excess base charge can be monitored using a split base structure. Conductance between the two split base electrodes is a linear function of collector current, independent of emitter current crowding, and its slope is directly proportional to base transit time.<<ETX>>