Sean N. Finegan

Non-overlapping super self-aligned BiCMOS with 87 ps low power ECL

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. A high-speed frequency divider, a multiplexer, and a demultiplexer operating up to 4.1 GHz, 5.5 Gb/s, and 6.2 Gb/s, respectively, have been fabricated. The results show that NOVA BiCMOS is suitable for Gb/s digital VLSI application.<<ETX>>

A technique for rapidly alternating boron and arsenic doping in ion‐implanted silicon molecular beam epitaxy

This letter reports the use of boron ion implantation doping during simultaneous growth of silicon molecular beam epitaxy. It describes further a technique for epitaxial growth of abrupt silicon p‐n junctions by rapid changeover during growth between boron and arsenic ion beams. This is expected to be of importance in a variety of applications, including, for example, high speed bipolar junction transistors.

An uncompensated silicon bipolar junction transistor fabricated using molecular beam epitaxy

The first silicon bipolar junction transistor fabricated using molecular beam epitaxy is reported. Epitaxial layers defining the collector, base, and emitter regions are grown successively at 850°C. Because no thermal diffusion steps are involved, junction location and base width are precisely defined. The final structure is mesa isolated using reactive ion etching. A peak forward current gain of 60 is measured. This technique is expected to be applicable to the development of very narrow base, ultrahigh speed bipolar transistors.

The design and characterization of nonoverlapping super self-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L/sub eff/=1.1 mu m and W/sub n//W/sub p/=10 mu m/10 mu m exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f/sub T/, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated. >

Nonoverlapping super self-aligned device structure for high-performance VLSI

The nonoverlapping super self-aligned structure (NOVA) is reported. Because of its nonoverlapping nature, this structure can be applied equally well to bipolar, CMOS, or BiCMOS processes. This structure effectively minimizes parasitic capacitance and resistance for both the MOS and bipolar devices. CMOS and bipolar devices are integrated into a high-performance BiCMOS technology. CMOS and emitter-coupled logic (ECL) ring oscillators with 1.5- mu m lithography are reported to have delays of 128 and 87 ps/stage, respectively.<<ETX>>

In-situ low energy BF 2 + ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF<inf>2</inf>+ in silicon molecular beam epitaxy (MBE) is described. BF<inf>2</inf>+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF<inf>2</inf>+-doped epitaxial material showed hard reverse breakdown characteristics.

Suppression of lateral autodoping from arsenic buried layer by selective epitaxy capping

An effective way to suppress lateral autodoping from the heavily arsenic-doped buried layer during silicon epitaxy is described. By using this simple technique, collector-substrate capacitance (C/sub cs/) is minimized. This process is ideal for high-speed BiCMOS and bipolar technology. A thin epilayer is first grown selectively on the buried layer. This selectively grown film suppresses the release of arsenic during the subsequent epi growth. High-performance bipolar devices have been fabricated in this epi material. Electrical measurements indicate that the crystalline quality is excellent.<<ETX>>

Lateral Autodoping Suppression by Selective Epitaxy Capping and Its Application in High Speed BiCMOS

fabrication. Other advanced technique like trench isolation may be considered. Trench isolation is, however, involved and expensive. A simple solution is to apply the recently reported selective epi growth (SEG)4-6). Fig.2 illustrates the process sequence. Single crystal silicon is selectively grown inside oxide windows. The highly doped buried layer is now capped. In addition, the oxide protects the off-buried layer region from the arsenic contamination. Subsequently, the oxide mask is removed and an epitaxy layer of desired doping is deposited. Lateral autodoping can be reduced by 2-3 orders of magnitude while maintaining a low arsenic buried layer sheet

Digital NMOS test circuits fabricated in silicon MBE

Integrated digital test circuits, as well as discrete NMOS devices, have been fabricated in epitaxial layers produced by silicon molecular-beam epitaxy (Si-MBE). The performance of these circuits and devices was found to be very similar to that of identical components processed in standard substrates. Unusually high low-field mobility was measured in the MBE MOSFETs.

1.5 mu m NOVA BiCMOS for Gb/s system application

BiCMOS technology which merges optimal CMOS and bipolar device structure is reported. Based on a nonoverlapping super-self-aligned structure (NOVA), the latest 1.5- mu m CMOS and ECL (emitter-coupled logic) ring oscillators have minimum delays of 110 ps/stage and 87 ps/stage, respectively. A frequency divider operating up to 4.6 GHz has been fabricated. A multiplexer and demultiplexer function up to 5.1 Gb/s. In addition to double self-alignments, a unique epi/isolation scheme combining lateral autodoping free epi deposition with a new fully recessed oxide process have been developed. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule.<<ETX>>