Tzyh-Cheang Lee

Demonstration of scaled Ge p-channel FinFETs integrated on Si

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/μm at 1V, 1.05 mS/μm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest gm/SS at Vdd=1V reported for non-planar unstrained Ge pFETs to date.

20nm gate bulk-finFET SONOS flash

High-performance FinFET SONOS (silicon-oxide-nitride-oxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved with high P/E speed (TP equiv 10mus and TE equiv 1ms), and a 1.5V window remained after 10 years at room temperature. Multi-level storage is also obtained with DeltaVt > 4V and TP,E equiv 1 ms. Operation voltages are not more than 7V in the two applications. Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines

Effects of germanium and carbon coimplants on phosphorus diffusion in silicon

The authors have studied the interactions between implant defects and phosphorus diffusion in crystalline silicon. Defect engineering enables ultrashallow n+∕p junction formation using phosphorus, carbon, and germanium coimplants, and spike anneal. Their experimental data suggest that the positioning of a preamorphized layer using germanium implants plays an important role in phosphorus diffusion. They find that extending the overlap of germanium preamorphization and carbon profiles results in greater reduction of phosphorus transient-enhanced diffusion by trapping more excess interstitials. This conclusion is consistent with the end-of-range defects calculated by Monte Carlo simulation and annealed carbon profiles.

Strain effect and channel length dependence of bias temperature instability on complementary metal-oxide-semiconductor field effect transistors with high-k/SiO2 gate stacks

The strain effect and channel length dependence of bias temperature instability on dual metal gate complementary metal-oxide-semiconductor field enhanced transistors with HfSiON dielectric were studied in detail. For channel length larger than 0.1 μm, both positive and negative bias temperature instabilities (PBTI and NBTI) were not affected by the tensile strain obviously. As the channel scaling down to less than 0.1 μm, the degradation after PBTI stress was still not influenced by the strain, however, the NBTI degradation was enhanced significantly. In addition, the dependence of BTI on channel length was extensively investigated under constant voltage and field stress.

Investigation of Bulk Traps Enhanced Gate-Induced Leakage Current in Hf-Based MOSFETs

A comprehensive study on bulk trap enhanced gate-induced drain leakage (BTE-GIDL) currents in high-MOSFETs is reported in this letter. The dependence of GIDL for various parameters, including the effect of Zr concentration in , high-film thickness, and electrical stress is investigated. The incorporation of Zr into reduces GIDL. GIDL was also found to reduce with thinner high-film. In addition, a significant correlation between GIDL and bulk trap density in high- film is established. Possible mechanisms were provided to explain the role of bulk trapping in BTE-GIDL, observed in high-devices.

A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivation

A novel technique to create a suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and the underlying silicon substrate is proposed for the first time to fabricate 28 nm p-metal–oxide–semiconductor field-effect transistors (p-MOSFET). Without Si surface passivation on the ESC, such an ESC structure could achieve a p-FET transconductance (Gm) gain of 26% higher and a better Ion–Ioff performance gain of 8% than that of conventional strained Si p-FETs with the source/drain (S/D) SiGe. Better S/D resistance (Rsd) in the resistance versus gate length plot and improved swing slope of the Id–Vgs plot indicates higher mobility in the ESC devices. Moreover, the off-state gate current of the ESC structure is also comparable to the conventional ones. From the x-ray photoelectron spectrum analysis, only the Si–O bonding, and no Ge–O bonding at the SiGe/SiO2 interface could account for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm p-MOSFET devices era.

Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes

We have fabricated FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved with a guiding layer. The self-assembly process is integrated with an existing CMOS process flow using conventional tools on a full wafer level. This is the first demonstration of functional circuits fabricated using self-assembly at the (n+1)th patterning level where n ≥ 1.

Relaxation-Free Strained SiGe with Super Anneal for 32nm High Performance PMOS and beyond

The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved

The influence of nitrogen incorporation on performance and bias temperature instability of metal oxide semiconductor field effect transistors with ultrathin high-k gate stacks

This paper reports a comprehensive study on the influence of nitrogen incorporation on high-k (HK) device performance and reliability. Two approaches including dielectric nitrogen annealing and interfacial layer (IL) nitrogen annealing are investigated. It is found the HK nitrogen annealing is a better solution for the trade-off between mobility and inversion oxide thickness than IL annealing. The positive bias temperature instability characteristic is improved by HK annealing. However, the HK nitrogen annealing lowers the barrier of dielectric and thus results in an abnormally high leakage current.