V. Bader

Through mold vias for stacking of mold embedded packages

The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm². The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components — whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating — all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular molding compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes.

High temperature potential of flip chip assemblies for automotive applications

Flip chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products as cellular phones or GPS devices. The upper temperature limits for such applications range from 80 /spl deg/C to a maximum of 125 /spl deg/C. To widen the application range of flip chip technology and to address the volume market of automotive and industrial electronics, the development of high temperature capable assemblies is crucial. Typical scenario for the integration of electronics into a car is a control unit in the engine compartment, where ambient temperatures are around 150 /spl deg/C, package junction temperatures may range from 175 /spl deg/C to 200 /spl deg/C and peak temperature may exceed these values. When using flip chip technology under high temperature conditions, major challenges are found in the application of interconnect media and supporting polymers. At elevated temperatures, the intermetallic phase formation of lead-free solders might lead to a reliability decrease, where polymeric materials as substrate and encapsulant do potentially show mismatched thermo-mechanical properties or material degradation and thus reliability is reduced. Literature does typically describe flip chip technologies behavior on organic substrates for consumer applications, but almost no information is available on the performance at temperatures beyond 125 /spl deg/C. Within the European project HOTCAR, dealing with high temperature electronics for automotive use in general, a German consortium consisting of an IC manufacturer (IFX), two technology users (Siemens VDO & Temic) and a research institute (Fraunhofer IZM) have cooperated to evaluate the high temperature potential of lead-free flip chip technology for automotive applications. According to automotive demands, an experimental study on the suitability of advanced Underfill encapsulants for high temperature has been performed. With the outcome of this pre-study, two promising underfill materials were selected and used in a test run with an automotive test vehicle. This comprises an automotive grade /spl mu/Controller mounted on a substrate manufactured according to automotive standards, as the major system components. Solder material used was SnAg with a Ni UBM in combination with two different substrate finishes NiAu and immersion Sn. These test devices were submitted to temperature cycles according to automotive specifications with a maximum temperature of 150 /spl deg/C. Intermetallic phase formation was studied after high temperature storage by cross sections and shear tests. Typical failure modes for flip chip failure have been identified and are described in detail. The experimental reliability investigations were backed by thermo-mechanical simulations. Taking advantage of the so-called submodelling technique, the solder joint behavior could be studied in detail for lead-free solders. Starting stress-free at 150 /spl deg/C, the calculations followed the real thermal cycling regime. As primary results, the accumulated equivalent creep strain and creep strain energy distributions were obtained. Based on Manson-Coffin-coefficients from recent experiments at IZM, mean cycles to failure (MCF) have been estimated for solder joint fatigue and compared with observed failure. In summary, a status of the high temperature potential of lead-free flip chip technology under automotive conditions is given and a first design guideline for high temperature automotive flip chip applications is provided.

Through mold via technology for multi-sensor stacking

With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8” to 12” in diameter, while future developments will deal with panel sizes up to 470 × 370 mm². The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components — whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating — all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lamination and were metalized together with the vias for chip interconnection. Reliability of the manufactured through mold vias with different via diameters and pitches was evaluated by moisture sensitivity level [MSL] testing, temperature cycling and humidity storage and test vehicles were analyzed both non-destructively and destructively. Results show high reliability potential of the introduced through mold via technology as samples have passed MSL 1 and more than 3000 temperature cycles and 3000 hour humidity storage without any electrical failure. The embedding and stacking technology is demonstrated for a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by the through mold vias and soldered to a base substrate. Concluding, within this paper on mold embedded SiPs both is shown — the development of TMVs, an advanced and low cost 3D packaging feature and demonstration of use of this feature for the assembly of a functional 3D multi-sensor system, illustrating the miniaturization potential of 3D system integration.

Water diffusion in micro- and nano-particle filled encapsulants

Polymer materials - mainly epoxy resins - are widely used in microelectronics packaging. They are established in printed circuit board manufacturing, for adhesives as die attach glues or for encapsulants as molding compounds, glob tops or underfill materials. Low cost and mass production capabilities are the main advantages of these materials. But like all polymers they cannot provide a hermetical sealing due to their permeability properties. The susceptibility to water diffusion through the polymer and along the interfaces is a drawback for polymer materials in general, as water inside a microelectronic package might lead to softening of the material and to a decreasing adhesive strength and resulting delaminations close to solder bumps or wire bonds reducing package reliability by decreasing the package structural integrity. During package reflow, the incorporated humidity might lead to popcorning, i.e. abrupt evaporation of humidity during reflow soldering. This effect is one major problem during plastic package assembly. The introduction of high temperature lead-free soldering processes has even increased this issue. Therefore, plastic packaging materials with enhanced humidity resistance would increase package reliability during assembly and lifetime ideally without cost increase and with no changes in processing.

Foldable Fan-Out Wafer Level Packaging

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A redistribution layer is applied on the reconfigured wafer and routes the die pads to the space around and on the die. After bump formation and package singulation by dicing an SMD compatible package is completed. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold vias or vertical interconnect elements [VIE] and a redistribution layer on both sides of the FOWLP. A Foldable Fan-out Wafer Level Package (FFOWLP) would now allow a single sided planar processing and yield a stacked three dimensional package by folding only. Folding can be implemented by a combination of a flexible redistribution layer and a dicing process that only cuts through the molding compound but leaves the redistribution layer untouched. As foldable redistribution layer e.g. polyimide can be used, a standard for flexible substrates. The feasibility of the proposed technology is demonstrated using a multi-chip package. Dies are mold embedded in wafer size. Subsequently the wiring is done by lamination of a polyimide film over the embedded components. In a process flow similar to conventional PCB manufacturing μvias are drilled to the die pads using a UV laser and metalized by Cu-electroplating. Conductor lines and pads are formed by Cu etching. A solder mask can be applied for pad definition. Finally, the wafer will be diced in two steps. First the bending cuts will be done by dicing only through the molding compound and in a second step package singulation will be carried out. Besides folding for package stacking the technology can be also be used to integrate multi-die packages into free form factor surfaces as bows, curves or defined angles. Upscaling of the technology described above from wafer to panel is also possible and offers low cost solutions and large/long foldable FOWLP stripes in a well-defined package.

Impact of RDL polymer on reliability of flip chip interconnects in thermal cycling — Correlation of experiments with finite element simulations

For WLP (Wafer Level Packaging) thin film polymers play a key role in respect to board level reliability. This paper introduces a reliability indicator giving a tendency of the polymer material to crack initiation around the UBM pad. This indicator derived from Finite Element simulated maximum stress in polymer layer and the material specific tensile strength. Comparing the simulation results with the experimental data we see the same impact of the mechanical material properties on the reliability. This proves the described reliability indicator as suitable for estimating thermal cycle reliability of RDL polymer materials gives application engineers and manufacturers a new tool for selecting the most suitable RDL material for e.g. flip chip and WLP applications.

Panel level packaging for LED lighting

General lighting by use of LED-Chips is one of the strongly growing markets today and also in future. One of the trends goes to LEDs with higher and higher luminous fluxes per chip area to get the best price per lumen on the market. Unfortunately, such large LEDs produce a lot of heat, which must be spread to avoid overheating and shorter lifetime of the LEDs. Another approach is the use of many small LEDs so that both light and heat source are spread into a larger area. Cost-effective established PCB-technology was applied to produce large-area light sources consisting of many small LED chips placed and electrically connected on a PCB-substrate. LEDs were ICA-bonded with their bottom pad to the PCB. The top contacts of the LEDs were established by laminating an adhesive copper sheet followed by a LDI structuring as known from PCB-via-technology. This assembly can then be completed by adding converting and light forming optical elements.

Nano- und micro sized filler particles for improved humidity resistance of encapsulants

Polymer materials - mainly epoxy resins - are widely used in microelectronics packaging. They are established in printed circuit board manufacturing, for adhesives as die attach glues or for encapsulants as molding compounds, glob tops or underfill materials. Low cost and mass production capabilities are the main advantages of these materials. But like all polymers they cannot provide a hermetical sealing due to their permeability properties. The susceptibility to water diffusion through the polymer and along the interfaces is a drawback for polymer materials in general, as water inside a microelectronic package might lead to softening of the material and to a decreasing adhesive strength and resulting delaminations close to solder bumps or wire bonds reducing package reliability by decreasing the package structural integrity. During package reflow, the incorporated humidity might lead to popcorning, i.e. abrupt evaporation of humidity during reflow soldering. This effect is one major problem during plastic package assembly. The introduction of high temperature lead-free soldering processes has even increased this issue. Therefore, plastic packaging materials with enhanced humidity resistance would increase package reliability during assembly and lifetime ideally without cost increase and with no changes in processing.

A novel and practical method for in-situ monitoring of interface delamination by local thermal diffusivity measurement

Today, there is no non-destructive, simple, inexpensive and yet accurate in-situ monitoring technique for cracks and delamination available for routine use in electronic package testing. However, such a method is highly desirable, as delamination testing is part of every qualification programme in industry. Rapid failure analytical techniques which allow introspect and easy-to-interpret information on adhesion loss during stress testing, analogous to e.g. resistance testing for solder joint reliability, would enable considerable speed up of the development process of advanced packaging technologies, especially also for situations where not even classical ex-situ methods like scanning acoustic microscopy or pulse phase thermography are applicable. So this paper proposes a radically new approach using local thermal impedance variations caused by cracks to generate electrically detectable signals by the 3ω-Method, designed as highly local thermal sensors array in analogy to a pixel matrix for readout as image from a delamination camera. We show the proof of concept of the method on an industry-grade flip-chip package, its robustness with respect to electrical readout and the very good correlation between experiment and simulation, enabling unequivocal detection of thermal impedance changes and its insensitivity to cross effects, e.g. moisture ingress. Guidelines and estimations for future applications are given.

Challenges and opportunities for Fan-out Panel Level Packing (FOPLP)

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12”/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18”×24” or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As an alternative process, lamination can be also considered. Already today PCB technologies offer the potential for large area panel packaging up to 24”×18”/610 × 457 mm2 and can be applied to form a redistribution layer [RDL] for large area reconfigured wafers or panels, replacing thin film redistribution. For PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using LDI techniques for maskless patterning. State of the art equipment and materials the manufacturing of structures down to 20 μm lines and spaces with a clear development trend to 10 μm lines and spaces and hence getting close to photolithography thin film structure sizes. Using the above mentioned maskless laser direct imaging technologies (LDI) instead of photolithography have a high potential for further cost reduction with intrinsic process advantages. The LDI cost advantage is backed by LDI availability for large panel sizes, also including 450 mm wafer form factors. Based on the technology described the Fan-out Panel Level Packaging approach will be demonstrated on full 24”×18”/610 × 457 mm2 format including large area assembly, embedding and redistribution. Related technology challenges as die shift, warpage, panel handling or yield will be discussed in detail. Using maskless LDI technology real die positions could be automatically adapted to the redistribution and hence less accurate die placement can be compensated and higher die shift could be tolerated which is a big advantage when moving towards large area with acceptable yield. In summary this paper describes the technological path from wafer level embedding to 24”×18” fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.