V. Paraschiv

10×10nm 2 Hf/HfO x crossbar resistive RAM with excellent performance, reliability and low-energy operation

We report on worlds smallest HfO2-based Resistive RAM (RRAM) cell to date, featuring a novel Hf/HfOx resistive element stack, with an area of less than 10×10 nm2, fast ns-range on/off switching times at low-voltages and with a switching energy per bit of <0.1pJ. With excellent endurance of more than 5.107cycles, large on/off verified-window (>50), no closure of the on/off window after 30hrs/200C and failure-free device operation after 30hrs/250C thermal stress, the major device-level nonvolatile memory requirements are met. Furthermore, we clarify the impact of film crystallinity on cell operation from a scalability viewpoint, the role of the cap layer and bring insight into the switching mechanisms.

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM): An area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window resistive switching cell

We report a novel self-compliant and self-rectifying resistive switching memory cell, with area-scalable switching currents, featuring a set current density of ~5nA/nm2 (<;9uA for a 40nm-size cell), high on-state half-bias nonlinearity of 102 and low reset current density of <;0.6nA/nm2 (<;1uA@40nm size). The cell can be operated at below ±4V/10ns, with a large on/off window of >102 and retention extrapolates to 10yr at 101°C. The switching stack is fully based on ALD processes, using common high-k dielectrics and has a thickness of <;10nm, meeting the 3D Vertical RRAM requirements. Moreover, we point out the nonlinearity-low-current operation interdependence and discuss the scaling potential of the areal switching RRAM for reliable sub-μA current operation in the 10nm-cell size realm.

A highly reliable 3-D integrated SBT ferroelectric capacitor enabling FeRAM scaling

Ferroelectric random access memories (FeRAMs) combine very attractive properties such as low-voltage operation, fast write and nonvolatility. However, unlike Flash memories, FeRAMs are difficult to scale along with the CMOS technology roadmap, mainly because of the decrease of available signal with decreasing cell area. One solution for further scaling is to integrate three-dimensional (3-D) FeCAPs. In this paper, we have integrated a 3-D FeCAP structure in a 0.35-/spl mu/m CMOS technology whereby the effective area of <1 /spl mu/m/sup 2/ single FeCAPs is increased by a factor of almost two. We show that, after optimization of the metal-organic chemical vapor deposition (MOCVD) deposition and post-anneal steps of the Sr/sub 0.8/Bi/sub 2.2/Ta/sub 2/O/sub 9/ (SBT) layer, the sidewall SBT contributes to the polarization Pr, resulting in higher Pr values for 0.81-/spl mu/m/sup 2/ three-dimensional (3-D) capacitors (2Pr/spl ap/15 /spl mu/C/cm/sup 2/) than for 1000 /spl mu/m/sup 2/ 2-D capacitors (2Pr/spl ap/10 /spl mu/C/cm/sup 2/). Moreover, these 3-D capacitors are observed to be fatigue-free and imprint-free up to 10/sup 11/ cycles (5-V square pulses), and extrapolations of retention tests indicate less than 10% Pr loss after ten years at 85/spl deg/C, which shows that sidewall SBT retains the same excellent reliability properties as 2-D capacitors. We demonstrate in this paper that the negative signal-scaling trend can be halted using 3-D FeCAPs. To our knowledge, this paper is the first report on electrical and reliability properties of integrated 3-D FeCAPs, and is a starting point for future development work on densely scaled FeRAMs.

SELECTIVE REMOVAL OF HIGH-K GATE DIELECTRICS

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. First, the fundamentals and limitations of both approaches are presented, then an overview of the existing experimental data is given. It is concluded that the best results could be obtained by combining the dry and wet approaches.

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

A-VMCO: A novel forming-free, self-rectifying, analog memory cell with low-current operation, nonfilamentary switching and excellent variability

We demonstrate a self-rectifying, compliance-free, BEOL CMOS-compatible, resistive switching memory device, with nonfilamentary switching mechanism, forming-free operation, analog switching behavior and excellent device to device operation uniformity, down to the smallest device size. The cells have a reset switching current density of ~0.3MA/cm2 (and ~10× lower set current). This corresponds to ~5uA reset current in a 40nm-size cell, projecting down to 1uA for a 20nm-size. The switching currents are tunable by process and structural cell design. The cells can be operated with pulses as short as 10ns, at below ±7V. Cycling for at least 106cy and retention of 55°C/3yr are demonstrated, with clear paths for further improvement. These key features are enabled by the use of an amorphous-Silicon (a-Si) barrier layer, which acts as a semi-insulating oxygen scavenger in a dual-layer a-Si/TiO2 active stack, being able to provide nonlinear IV cell characteristics, as well as to induce a large oxygen vacancy density in the switching layer.

Influence of crystallographic orientation on dry etch properties of TiN

A study of the impact of physical vapor deposition conditions on the etch properties of TiN has been conducted using a transformer coupled plasma. This work focuses only on a Cl2-based etch plasma. It is shown that the crystallographic orientation of TiN, observed from x-ray diffraction spectra, has a major influence on the etch behavior. Etch yields at varying dry etch conditions of two types of TiN, with different crystallographic orientations, have been studied quantitatively. The high roughness which is created during plasma exposure was identified as being the result of different etch rates of grains and intergranular material at the grain boundaries. Moreover, it is shown that TiN(111) is more difficult to etch, resulting in more pronounced roughness, than TiN(200), which is easier to etch, resulting in smoother surfaces for certain process conditions.

Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

Here for the first time we discuss RRAM cell performance and reliability through process improvement. Excellent post-cycling (106) retention and post-bake retention and endurance have been achieved for the optimized process conditions. The optimized RRAM cells show potential for manufacturability and scalability for high density memory application.