Vincent W. Leung

A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications

An improved envelope amplifier architecture for envelope tracking RF power amplifiers is presented, consisting of two switching amplifiers and one linear amplifier. The first switching amplifier and the linear amplifier provide wideband and high-efficiency operation, while the second switching amplifier provides a reduced bandwidth variable supply to the linear amplifier to further reduce power loss. The first switching amplifier and the linear amplifier are fabricated together in a 150 nm CMOS process, while the second switching amplifier is external. Measurements show a maximum average efficiency of 82% for a 10 MHz LTE signal with a 6 dB PAPR at 29.7 dBm output power and an SFDR of 63 dBc for a single tone of 5 MHz driving an 8 Ω load.

A Wideband CMOS/GaAs HBT Envelope Tracking Power Amplifier for 4G LTE Mobile Terminal Applications

A high-efficiency envelope tracking power amplifier for long-term evolution (LTE) handset mobile terminals is presented. The envelope amplifier consists of a wideband buffered linear amplifier as a voltage source and a hysteretically controlled switching amplifier as a dependent current source. The linear amplifier has a high current drive capability of approximately 500 mA while consuming only 12 mA of quiescent current. The impact of envelope shaping on system efficiency and stability is investigated. The envelope amplifier is implemented in a 0.15- μm CMOS process and tested with a GaAs HBT RF power amplifier. For a 20-MHz LTE signal with 6.6-dB peak-to-average power ratio, an overall efficiency of 43% is achieved at 29-dBm RF output power level with relative constellation error below 1.9% after digital pre-distortion.

Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortion

Adaptive bias techniques based on envelope signal power detection have been proposed for linearity enhancement and dc current reduction in RF amplifiers. Experimental results show an improvement in amplifier linearity, although asymmetric intermodulation distortion (IMD) was observed. This work rigorously studies the effects of the envelope signal injection on amplifier distortion using the Volterra series formulations. The results intuitively explain the spectral regrowth asymmetry, and point to a design technique in which third-order IMD can be optimally cancelled. The theory was verified through comparison to measurement and simulation results.

Digital-IF WCDMA handset transmitter IC in 0.25 /spl mu/m SiGe BiCMOS

Implemented in a 0.25-/spl mu/m SiGe BiCMOS process, a highly integrated low-power transmitter IC (TxIC) is developed for wideband code-division multiple-access handset applications. Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion scheme. The TxIC features a low-power high-speed D/A converter designed to drive a dominantly capacitive load. For the upconversion mixer and the RF amplifier, adaptive biases are designed to minimize the quiescent power consumption and to provide current boost only when needed. The TxIC achieves <1% EVM. It consumes 180 mW (3-V supply) for the maximum output power of +5 dBm and reduces to 120 mW during power backoff.

High efficiency envelope tracking power amplifier with very low quiescent power for 20 MHz LTE

A high efficiency wideband envelope tracking power amplifier with low quiescent power is presented. The CMOS envelope amplifier has a combined linear amplifier and switching amplifier to achieve high efficiency and wider bandwidth. Quiescent power of the envelope amplifier is reduced using a source cross-coupled linear amplifier with inherently low DC power dissipation. Measurements show a power added efficiency of 45% for the envelope tracking power amplifier for 20 MHz LTE signal with 6.0 dB PAPR at 2.5 GHz at 1W output power.

Digital-IF WCDMA handset transmitter IC in 0.25-μm SiGe BiCMOS

Implemented in a 0.25-μm SiGe BiCMOS process, a highly integrated low-power transmitter IC (TxIC) is developed for wideband code-division multiple-access handset applications. Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion scheme. The TxIC features a low-power high-speed D/A converter designed to drive a dominantly capacitive load. For the upconversion mixer and the RF amplifier, adaptive biases are designed to minimize the quiescent power consumption and to provide current boost only when needed. The TxIC achieves <1% EVM. It consumes 180 mW (3-V supply) for the maximum output power of +5 dBm and reduces to 120 mW during power backoff.

An improved wide-dynamic range tunable RF interference suppression notch filter

A tunable RF filter for interference suppression applications, using a balanced passive complex mixer and a parallel LC tank load, is presented. The circuit has very wide dynamic range and zero dc-power consumption, and is designed for cognitive radio applications in the IEEE 802.22 system.

Improved digital-IF transmitter architecture for highly integrated W-CDMA mobile terminals

An improved digital intermediate frequency (IF) transmitter architecture for wide-band code-division multiple-access (W-CDMA) mobile terminals is proposed. Based on the heterodyne design but without requiring any off-chip IF filter, the transmitter enjoys the advantages of a homodyne architecture (such as circuit simplicity, low power consumption, and a high level of integration) while avoiding the performance problems associated with direct upconversion. By implementing the quadrature modulation in the digital domain and requiring only a single path of analog baseband circuits, inherently perfect I/Q matching and good error vector magnitude (EVM) performance can be achieved. The IF is chosen to be a quarter of the clock rate for a very simple and low-power digital modulator design. The difficulties of on-chip IF filtering were greatly alleviated by 1) performing a careful frequency planning and 2) employing a special-purpose digital-to-analog converter to produce high-order sin(x)/x rolloff. System-level simulation demonstrates that spurious-emission requirements are met with virtually no dedicated reconstruction filter circuits. This architecture takes full advantage of complimentary metal-oxide-semiconductor technology scaling by employing digital processing to ease analog complexities.

Signal generation algorithm for digital polar transmitters with reduced receive band noise

Digital polar transmitters are under development for multiband handset applications, but typically lead to excess Rx band noise (RxBN). In this paper, a technique to improve the RxBN of a digital polar transmitter is demonstrated. Linear phase FIR filters are applied to both envelope and phase signals, so that the RxBN becomes relatively insensitive to transmitter non-idealities. At the same time, there is only small degradation of ACLR and EVM. Noise shaping algorithms are also applied to reduce the envelope quantization noise. For a WCDMA signal at 1.75 GHz, with a corresponding Rx band at 1.845 GHz, we demonstrate RxBN of -142 dBm/Hz in simulation and -125 dBm/Hz in experimental measurements.

A 1–3 GHz Delta–Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

This paper presents a new fully digital architecture for an RF phase modulator with significantly improved phase resolution. The modulator utilizes 32 variable delay-lines in a delay-locked loop (DLL) configuration to provide 1–3 GHz operation with coarse 5-bit resolution. A 5-bit low-glitch multiplexer with accurate delay control on the control lines is used to select different taps of the DLL according to the baseband digital phase data to generate the desired phase modulated signal at the output. To further increase the effective resolution, a high speed 10-bit input, 5-bit output digital delta–sigma modulator (DSM) is added in front of the multiplexer. The DSM compensates for the phase truncation occurring in the 5-bit DLL. The impact of delay mismatch and phase offset in the DLL on the phase modulator output performance are studied. The phase modulator IC is implemented in 45-nm CMOS SOI and achieves <2% rms EVM together with 55-dB rejection of close-to-carrier emissions for an 8-Mb/s GMSK signal at 2.3 GHz, with power consumption below 35 mW.