W. H. Zisser

Effects of the initial stress at the bottom of open TSVs

In this work we have studied delamination in Open Through Silicon Vias structures under different initial stress loads. The study has been carried out by means of simulation which is based on the evaluation of the J integral for different interfaces. Our simulations enabled us to determine the structures with the lowest failure probability.

Analysis of electromigration void nucleation failure time in open copper TSVs

Through silicon vias (TSVs) are innovative interconnects which provide wider functionality and higher performance per unit area in three-dimensional (3D) integrated circuits. The reliability of TSVs in integrated circuits constitutes an important issue in microelectronics. One of the most relevant degradation mechanisms in interconnects is electromigration (EM). Therefore, the prediction of the EM failure behavior is a crucial necessity. Traditionally, Blacks equation has been used from the early times of EM investigations for the estimation of the time to failure (TTF) for a wide spectrum of different interconnects. In this work we investigate the applicability of Blacks equation for the estimation of the EM failure time in open copper TSV technologies. The EM void nucleation model has been solved by numerical calculations. Simulations have been carried out for different current densities. The results are in good agreement with Blacks equation.

Factors that influence delamination at the bottom of open TSVs

We have analyzed how the mechanical and geometrical parameters of the Open Through Silicon Vias influence failures induced by delamination of the interfaces. Through Silicon Vias are the units of the interconnection structure that establish the connection through the silicon die. We show that there are different factors that influence the failure of the device by analyzing the effect of external forces and different thicknesses of the layers on delamination. From our simulations we found how the mechanical and geometrical parameters influence the Energy Release Rate and therefore the probability of delamination.

Electromigration induced resistance increase in open TSVs

Through silicon vias are the components in three-dimensional integrated circuits, which are responsible for the vertical connection inside the dies. In this work we present studies about the reliability of open through silicon vias against electromigration. A two-step approach is followed. In the first step the stress development of a void free structure is analyzed by means of simulation to find the locations, where voids due to stress are most probably nucleated. In the second step, voids are placed in the through silicon vias and their evolution is traced including the increase of resistance. The resistance raises more than linearly in time and shows an abrupt open circuit failure. Simulations were carried out for different currents and fitted to Blacks equation. These results are in good agreement with results of time accelerated electromigration tests.

Electromigration reliability of open TSV structures

A study of electromigration in open through silicon vias is presented. The calculations are based on the drift-diffusion model for electromigration combined with mechanical simulations. The results show that the highest stresses are located at the aluminium/tungsten interfaces, near the region where the electrical current is introduced into the open through silicon vias, which happens to be the location of the highest current density at the interface. There, the electromigration induced degradation, e.g. void nucleation, is most probable to occur.

Modeling electromigration in nanoscaled copper interconnects

In this work we present an approach to modeling grain boundaries and material interfaces in nanoscaled copper interconnects. Using a sample structure with a 40nm×40nm cross section and an applied current density of 1MA/cm2, we perform a comparative analysis while ignoring or including grains, with an average grain size of 50nm. The novelty in our approach is the treatment of microstructure interfaces using a binary parameter, which is further used to define interface-specific material properties for copper resistivity and electromigration modeling. Our models show that the inclusion of microstructure effects results in an increased resistance, increased vacancy migration, and ultimately in a higher EM-induced stress.

Stress Evolution During Nanoindentation in Open TSVs

We applied a nanoindentation technique in an open through silicon via structure by means of simulations. During nanoindentation, a spherical diamond indenter penetrates into the device by applying a force. This penetration causes displacement and deformation of the materials. The simulation results were compared with experimental data, as loading force versus penetration depth. Consequently, we estimated the areas in the structure, in which a mechanical failure due to an external load can be expected. Our simulations revealed the regions with the highest concentration of mechanical stress. These are the critical areas in which the probability of device failure, such as cracking or delamination, is at its highest.

Electromigration in solder bumps: A mean-time-to-failure TCAD study

The mechanical and electrical properties of solder bumps influence the overall reliability of 3D ICs. A characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation is enhanced by electromigration and leads to the formation of voids which can cause a complete failure of a solder bump. In this paper we present a compact model for prediction of the mean-time-to-failure of solder bumps under the influence of electromigration.

Modeling of microstructural effects on electromigration failure

Current electromigration models used for simulation and analysis of interconnect reliability lack the appropriate description of metal microstructure and consequently have a very limited predictive capability. Therefore, the main objective of our work was obtaining more sophisticated electromigration tools. The problem is addressed through a combination of different levels of atomistic modeling and already available, continuum level macroscopic models. A novel method for an ab initio calculation of the effective valence for electromigration is presented and its application on the analysis of EM behavior is demonstrated. Additionally, a simple analytical model for the early electromigration lifetime is obtained. We have shown that its application provides a reasonable estimate for the early electromigration failures including the effect of microstructure. A simulation study is also applied on electromigration failure in tin solder bumps, where it contributed the understanding of the role of tin crystal anisotropy in the degradation mechanism of solder bumps.

Electromigration induced stress in open TSVs

A study of electromigration in open through silicon vias (TSVs) is presented. The calculations are based on the drift-diffusion model for electromigration combined with mechanical simulations. The results show that the highest stresses are located at the aluminium/tungsten interfaces, near the region where the electrical current is introduced into the TSV, which happens to be the location of the highest current density at the interface there, the electromigration induced degradation, e.g. void nucleation, is most probable to occur.