Roberto Lacerda de Orio

An analytical approach for physical modeling of hot-carrier induced degradation

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.

Effects of sidewall scallops on the performance and reliability of filled copper and open tungsten TSVs

The effects of the presence of scallops along the sidewalls of filled (copper) and open (tungsten) TSVs are studied. The Bosch process is used in order to generate highly vertical deep trenches; however, the process results in scallops along the etched sidewalls. A model for the Bosch process is implemented in an in-house level set simulator in order to generate various TSV structures with small and large sidewall scallops. The resulting geometries are imported into a finite element tool in order to analyze the performance and reliability of the devices. The electrical parameters of the TSVs are shown to vary when scallops are present for both types of TSVs. In addition, the maximum thermo-mechanical stress increases in the presence of scallops, while the average stress along the interfaces remains relatively unchanged. Electromigration analyses were also performed on the structures in order to determine stress development during the early stages of operation. It was found that the filled TSV with scalloped sidewalls experiences a higher current density and suffers from increased stress, while the sidewall scallops do not cause variation in the stress of open tungsten TSVs. The open tungsten TSVs experience most Electromigration-induced stress in the connecting metal layers and not along the sidewall.

Interconnect reliability dependence on fast diffusivity paths

The reliability of interconnects in modern integrated circuits is determined by the magnitude and direction of the effective valence for electromigration (EM). The effective valence depends on local atomistic configurations of fast diffusivity paths such as metal interfaces, dislocations, and the grain boundary; therefore, microstructural variations lead to a statistically predictable behavior for the EM life time. Quantum mechanical investigations of EM have been carried out on an atomistic level in order to obtain numerically efficient methods for calculating the effective valence. The results of ab initio calculations of the effective valence have been used to parametrize the continuum-level EM models. The impact of fast

The Effect of Microstructure on Electromigration-Induced Failure Development

The effect of the microstructure on the electromigration failure development is analyzed. We investigate the influence of the statistical distribution of copper grain sizes on the electromigration time to failure distribution. Also, the effect of the microstructure on the formation and development of an electromigration-induced void is studied by simulation and the results are compared with experiments. It is shown that the lognormal distribution of the grain sizes resulted in lognormal distributions of the electromigration lifetimes. A close investigation has shown that the network of grain boundaries has a decisive impact in the determination of void nucleation sites and main features of void development.

The Effect of Copper Grain Size Statistics on the Electromigration Lifetime Distribution

We investigate the influence of the statistical dis- tribution of copper grain sizes on the electromigration time- to-failure distribution. We have applied a continuum multi- physics electromigration model which incorporates the effects of grain boundaries for stress build-up. The peak of tensile stress develops at the intersection of copper grain boundaries with the capping layer. It is shown that the electromigration lifetimes follow lognormal distributions. Moreover, the increase of the standard deviation of the grain size distribution results in an increase of the electromigration lifetimes standard deviation. The results strongly imply that the lognormal distribution of the grain sizes is a primary cause for the lognormal distribution of electromigration lifetimes.

Modeling Electromigration Lifetimes of Copper Interconnects

A model for early failure due to electromigration in copper dualdamascene interconnects is proposed. The model is based on analytical expressions obtained from solutions of electromigration stress build-up assuming slit void growth under the interconnect vias. It is demonstrated that the model satisfactorily describes the complex physics of void nucleation and growth of the electromigration damage. Furthermore, it is shown that the simulation results provide reasonable estimates for early electromigration failures.

Copper Microstructure Impact on Evolution of Electromigration Induced Voids

We study the impact of microstructure on nucleation and evolution of electromigration induced voids. The grain boundaries are described with a comprehensive model which includes the dynamics of mobile and immobile vacancies in dependence of mechanical stress. The surface of an evolving void is modeled by a three-dimensional Level-Set algorithm. Simulations have shown that the constellation of grain boundaries determines the electromigration failure behavior seriously. I. INTRODUCTION Contemporary integrated circuits are often designed using simple and conservative design rules to ensure that the re- sulting circuits meet reliability goals. This precaution leads to reduced performance for a given circuit and metallization technology. An ultimative hope of integrated circuits designers today is to have a computer program at hand, which predicts the behavior of thin film metalizations under any imaginable condition. Due to intensive development in the last decade, physical models of electromigration have reached a level of maturity, which enables predictions of failure behavior. The cause of failure is always an electromigration induced void in the interconnect structure. We present our recent development in modeling of void nucleation and void evolution. A new model for grain boundary physics is applied as extension and refinement of the standard electromigration continuum model. The model differentiates between mobile and immobile vacancies. Immobile vacancies are captured at grain boundaries and triple points, causing a build-up of tensile stress. High tensile stress leads to nucleation of intrinsic voids. These voids evolve through the interconnect causing a resistance change and, occasionally, a complete failure. Different approaches have been applied to model evolving void surfaces in the last ten years. However, all of these mod- els lack an appropriate description of the void development process, neglecting relevant physical phenomena that lead to interconnect failure. Moreover, these models are only suitable for simulations of simple two-dimensional interconnects and cannot realistically describe the void evolution mechanisms in modern complex interconnect structures. In this paper a three-dimensional Level-Set module is applied to simulate the evolving void surface. The site of void nucleation and the morphology of the evolving void accurately reproduce experimental observations.

Formation and movement of voids in copper interconnect structures

Electromigration (EM) is one of the main reliability concerns in copper interconnects. In particular, it is a critical issue for new emerging technologies, such as through silicon via (TSV) technology. In this work the impact of formation and growth of voids under a TSV located at the cathode end of a typical dual-damascene line is analyzed. The resistance change of the structure is numerically simulated and modeled. It is shown that there exist two modes of resistance development caused by large and small voids.

Electromigration failure development in modern dual-damascene interconnects

The electromigration failure development in typical copper dual-damascene interconnect structures is analyzed based on numerical simulations. The origin of the lognormal distribution of electromigration times to failure is investigated. Also, electromigration-induced void formation and evolution in advanced 0.18 µm dual-damascene lines are simulated and the results are compared with experiments. It is shown that the lognormal distribution of the grain sizes leads to lognormal distributions of the electromigration lifetimes. Moreover, the void nucleation sites and main features of void development are highly dependent on the microstructure of the interconnect lines.

Analysis of Electromigration in Dual-Damascene Interconnect Structures

The effects of grain boundaries on electromigration failure are presented. The electromigration model incorporates the grain boundary as a separate medium which acts not only as fast diffusivity path for material transport but also absorbs and releases vacancies. Moreover, we analyze the void nucleation condition and its implication on electromigration failure is discussed. Our results show that high stress and a high vacancy concentration develop at the triple points formed on the interface between copper grains and the capping layer, where a void nucleation is likely to take place. This scenario of weak triple points in combination with a stress threshold also supports the mechanism of multiple void nucleation as it has been experimentally observed.