A. Van den Bosch

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters

Although very high update rates are achieved in recent publications on high resolution D/A converters, the bottleneck in the design is to achieve a high spurious free output signal bandwidth. The influence of the dynamic output impedance on the chip performance has been analyzed and has been identified as an important limitation for the spurious free dynamic range (SFDR) of high resolution DACs. Based on the presented analysis an optimized topology is proposed.

An accurate statistical yield model for CMOS current-steering D/A converters

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

A 12 bit 200 MHz low glitch CMOS D/A converter

A 12-bit 200 MHz CMOS current steering D/A converter is presented. The measured glitch energy is 0.8 pVs. To obtain this very low glitch energy specification, a new driver circuit using a dynamic latch is proposed. The measured INL is better than +/-0.5 LSB. The D/A converter operates at a 2.7 V power supply, it has a 20 mA full swing output current and a 200 MHz conversion rate. The worst case power consumption is 140 mW at the maximum conversion rate. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

A 12 b 500 MSample/s current-steering CMOS D/A converter

This 12b 500MSample/s CMOS current-steering D/A converter has a segmented architecture. The 5MSBs are converted using the unary approach. A fully custom-made thermometer decoder is manually laid out to achieve the 500MSample/s update rate. The 7LSBs are converted using the binary approach, where the digital input bits directly control the switches. To minimize latency problems and to optimize dynamic performance, a dummy decoder is inserted between the inputs and the switch transistors. Using this architecture, a trade-off between good static specifications and moderate power complexity of the DAC is achieved.

Systematic design of high-accuracy current-steering D/A converter macrocells for integrated VLSI systems

This brief presents a systematic design methodology for digital-to analog (D/A) converter macrocells for integrated VLSI systems. A generic behavioral model is included for system level exploration to define the converters specifications. The architecture and the sizes of the devices are then calculated using a performance-driven design methodology. Using a novel layout tool, the layout of the regular structures with complex connectivity, typical for D/A converters, is automatically generated. Finally, a detailed behavioral model is extracted, combining both complex dynamic behavior (glitch energy) and static behavior. A 12-bit and two 14-bit D/A converters have been designed using this approach. It is demonstrated how the applied methodology and supporting tools drastically reduce the total design time, thereby significantly increasing analog design productivity.

A high-density, matched hexagonal transistor structure in standard CMOS technology for high-speed applications

In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance caused by the small area. The matching properties of this structure have been investigated, and these results have been compared with those for traditional finger-style structures. Exploiting the advantages, these transistors are very well suited for high-speed applications with a demand for both good matching and a small area, such as multibit current steering D/A converters or wireless applications. The test chips have been implemented in a standard 0.5-/spl mu/m CMOS technology. No adaptations to the standard technology have been made to realize the structures.

Randomized clinical trial of laparoscopic colectomy with or without natural‐orifice specimen extraction

Although conventional laparoscopic colectomy is a validated technique, laparoscopic natural‐orifice specimen extraction (NOSE) colectomy might improve outcome. This randomized clinical trial compared analgesia requirements, postoperative pain, anorectal function, inflammatory response and cosmesis in laparoscopic NOSE colectomy and conventional laparoscopic colectomy.

A low power, 10-bit CMOS D/A converter for high speed applications

In this paper, the realization of a fully binary 10-bit current steering CMOS DAC is presented. Both the measured INL and DNL are smaller than 0.2 LSB. Better than 60 dB SFDR is achieved for all output signals up to a 30 MS/s Nyquist frequency. For a 1 MHz signal, the chip achieves better than 60 dB SFDR for all update rates up to 800 MS/s. The presented DAC core occupies 0.23 mm/sup 2/. The digital power consumption is only 1 mW for a 30 MS/s Nyquist operation. Based on a fundamental theoretical INL- and DNL-yield analysis, the presented design explores the limits towards the binary and the low-power edges of the design space.

A 12 b accuracy 300 Msample/s update rate CMOS DAC

Of several technology and architecture alternatives for >100 MHz >10 b DACs, CMOS current-steering DAC architectures are particularly suitable. (1) They can be designed in a standard digital CMOS technology, with evident cost and power consumption advantages in the integration with the digital circuits, and (2) They are intrinsically faster and more linear than competing architectures such as resistor-string DACs. This DAC is integrated in a standard digital 0.5 /spl mu/m CMOS technology. It has a current steering 6+2+4 segmented architecture: first, the six most significant bits (MSBs) are linearly decoded; second, the intermediate two bits are also linearly decoded, but independently from the MSBs; third, the four least significant bits are binary weighted.