Walter H. Henkels

A 500-MHz, 32-word/spl times/64-bit, eight-port self-resetting CMOS register file

A two-write-port, six-read-port, 32/spl times/64-bit register file has been designed for 2.5-V 0.5-/spl mu/m CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84/spl times/1.55 mm/sup 2/, and the cell size is 21.6/spl times/30 /spl mu/m/sup 2/. The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs.

A pulse-to-static conversion latch with a self-timed control circuit

The design and experimental demonstration of a low-power pulse-to-static conversion latch circuit is described. The circuit includes self-timed control and a 64-bit latch array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with SRCMOS test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance. An experimental 64-bit latch array and self-timed control macro, designed for 2.5 V-0.5 /spl mu/m CMOS technology, has been successfully fabricated and tested. The full circuit occupies an area of 1.704 mm/spl times/0.07 mm, and the size of latch bit cell is 21.6 /spl mu/m/spl times/70 /spl mu/m. Experimental results have shown the conversion latch to function properly, capturing 1.2 ns output pulses from an SRCMOS register file, and properly converting them to static levels. The measured delay from global clock to static output was 725 ps.

An experimental 64-bit decoded Josephson NDRO random access memory

The design and testing of an experimental fully decoded 64-bit Josephson NDRO (nondestructive readout) RAM chip are described. Tree decoders were used to access the memory cells. The basic memory cell was a ring cell containing a single write gate. The chips were built in a coarse 25 /spl mu/m technology since neither speed nor density were stressed in this study. An access time of 4 ns with full margins and of 2.3 ns with reduced margins were demonstrated. The corresponding full memory cycle times were 5 and 3.5 ns, respectively. Good agreement with computer simulations was obtained throughout.

A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb*4, 78-mm/sup 2/ chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25 degrees C, and 50-pF load. A 256-b*4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 mu m n-well CMOS process. >

Experimental single flux quantum NDRO Josephson memory cell

Single flux quantum nondestructive readout (NDRO) Josephson memory cells which store an energy of only ~6/spl times/10/SUP -20/ J have been successfully fabricated and operated for the first time. Margin enhancement due to quantization, and low operating currents render this cell an attractive basis for a <1 ns access-time Josephson cache memory designed with a 2.5 /spl mu/m technology.

Large-signal 2T, 1C DRAM cell: signal and layout analysis

This paper presents a general signal and layout analysis for the two-transistor, one-capacitor DRAM cell. The 2T, 1C configuration enables significantly larger, typically /spl gsim/3x, raw sense-signal than is achievable in conventional 1T, 1C cells. In general, stray capacitances at the capacitor nodes further increase the signal level; an exact analytic formula is derived in this case, including the dependence upon bitline precharge level. With trench technology, the 2T, 1C cell occupies 25-30% more area than a corresponding folded-bitline 1T, 1C cell; an implementation employing a buried strap is proposed. Maximization of array density requires multiplexing bitlines to sense amps. >

A 12-ns low-temperature DRAM

A 12-ns access-time 0.5-Mb CMOS DRAM (dynamic random-access memory) operated at liquid-nitrogen temperatures is discussed. Comprehensive measurements, featuring a low-temperature e-beam tester, focused on circuit concerns particularly relevant to high speed. The results, including the first reported measurements of soft error rate (SER) at low temperatures, show that noise, power, and SER do not preclude very high-speed liquid-nitrogen DRAM operation. >

A 4 Mb Low-temperature DRAM

The authors present the characterization of the first dynamic RAM (DRAM) fabricated in a technology specifically optimized for cryogenic operation. With the power supply adjusted to assure hot-electron reliability, the 25-ns 4-Mb low-temperature (LT) chips operated 3 times faster than conventional chips. The LT-optimized chips functioned properly with cycle times as fast as 45 ns, and with a toggle-mode data rate of 667 Mb/s. Wide operating margins and a very large process window for data retention were demonstrated. At a temperature of 85 K the storage retention time of the trench-capacitor memory cells exceeded 8 h. This study shows that the performance leverage offered by low temperature applies equally well to DRAM and to logic. There is no limitation inherent to memory. >

Low temperature SER and noise in a high speed DRAM

The soft error rate (SER) and power bus noise were measured for a high-speed 512 kb CMOS DRAM (dynamic random access memory) operated at liquid-nitrogen temperatures. The SER decreased by about 3-20 times, depending upon cycle time and data type, and the power bus noise increased, but only modestly, at low temperature. These results show that the noise and SER do not preclude high-speed cryogenic DRAM operation. Compensation of increased inductive noise by decreased resistive noise is found to be a significant advantage in obtaining speed improvement by temperature reduction, rather than by room-temperature circuit and device techniques.<<ETX>>

Internal node probing of a DRAM with a low-temperature e-beam tester

In order to measure signals on internal nodes of circuits operated at liquid-nitrogen temperature, all electron-beam (e-beam) tester has been modified to cool circuits to this temperature during test. This apparatus has made it possible to measure signals on internal nodes of a high-speed DRAM operated at low temperature. The waveforms, which cannot be measured by other methods, provide the only means of determining the internal operation of the circuit. The instrument is described, and measurements of some critical DRAM signals are presented. In particular, the constancy of the bit-line equalization level, is shown, and observations of the interrelationship between power supply voltage, power bus noise, access time, and temperature are reported. >