Wei Lee

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.

On the prediction of geometry-dependent floating-body effect in SOI MOSFETs

This brief demonstrates that, through the perspective of body-source built-in potential lowering (/spl Delta/V/sub bi/), the geometry-dependent floating-body effect in state-of-the-art silicon-on-insulator (SOI) MOSFETs can be explained and predicted by the geometry dependence of threshold voltage (V/sub T/). The correlation between /spl Delta/V/sub bi/ and V/sub T/ unveiled in this brief is the underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip.

On the Experimental Determination of Channel Backscattering Characteristics—Limitation and Application for the Process Monitoring Purpose

This paper reports a generalized temperature-dependent channel backscattering extraction method that can self-consistently determine the temperature sensitivity of the low-field mobility and the critical length in nanoscale MOSFETs. Through comparing the gate voltage and temperature dependence, we have shown that assuming constant temperature sensitivity of the low-field mobility and the critical length will result in unphysical backscattering characteristics. We have also investigated the limitation in this self-consistent method and proposed guidelines for experimental extraction. Our results show that channel backscattering is increased for NMOSFETs with higher body doping and HfO2 dielectric and can be reduced for PMOSFETs when the process-induced uniaxial compressive strain technology is employed. This paper indicates that the self-consistent temperature-dependent method is competent to be routinely used in technology development for the process monitoring purpose.

Investigation of Anomalous Inversion C – V Characteristics for Long-Channel MOSFETs With Leaky Dielectrics: Mechanisms and Reconstruction

This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (Rii). The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (~95% for L = 20 mum) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.

Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4

In this work, we investigate the distorted C-V characteristics for MOSFETs with ultra-thin gate oxide. We propose a scalable BSIM4-based macro model to simulate the anomalous C-V behavior. Based on the model, we develop a methodology to extract the true MOS capacitance.

An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature

To allow high-temperature operation, the size of the SET needs to be further reduced (Peters et al., 1998). The suppression of short-channel effects, therefore, is especially critical to enabling single-electron tunneling at elevated temperature in the scaled MOSFET. In this work, we control the short-channel effect for devices with gate length down to 30 nm using thin oxide and multiple-gate SOI structures. We conduct an assessment of single-electron effects in our multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

Source/drain series resistance induced feedback effect on drain current mismatch and its implication

We have reported and modeled a new source/drain series resistance induced feedback effect on the drain current mismatch of aggressively scaled MOSFETs. This feedback effect needs to be considered when one-to-one comparisons between Si and high-mobility channel (e.g., Ge) devices regarding intrinsic drain current variability are made.

Investigation of channel backscattering characteristics for nanoscale SOI MOSFETs using a new temperature-dependent method

In this work, we investigate the channel backscattering characteristics for SOI MOSFETs using a new temperature-dependent method with consideration of self-heating effects. The temperature sensitivity of mobility (beta, mu0propTbeta) is self-consistently determined along with the backscattering coefficient rsat.

A comprehensive study of single-electron effects in multiple-gate MOSFETs

In this paper, an in-depth study of single-electron effects in multiple-gate SOI MOSFETs had been conducted. The impact of quantum mechanical effects on Coulomb blockade oscillations has been investigated. The study indicated that, to enable room-temperature SET applications, raising the gate-dot coupling strength and the access resistance were crucial. The multiple-gate SOI MOSFET with the non-overlapped architecture was an attractive approach for future SETs.

Investigation of inversion capacitance-voltage reconstruction for metal oxide semiconductor field effect transistors with leaky dielectrics using BSIM4/SPICE and intrinsic input resistance model

This paper presents an inversion capacitance–voltage (C–V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (Rii) model. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Since the Rii model is scalable with VGS and L, our Rii approach is physically accurate. Due to its simplicity, this method may provide an option for regular process monitoring purposes.