Wei-Tsu Tseng

Comparison of Cu electromigration lifetime in Cu interconnects coated with various caps

Electromigration in Cu Damascene lines with bamboo-like grain structures, either capped with Ta/TaN, SiNx, SiCxNyHz layers, or without any cap, was investigated. A thin Ta/TaN cap on top of the Cu line surface significantly improves electromigration lifetime when compared with lines without a cap and with lines capped with SiNx or SiCxNyHz. The activation energy for electromigration increased from 0.87 eV for lines without a cap to 1.0–1.1 eV for samples with SiNx or SiCxNyHz caps and to 1.4 eV for Ta/TaN capped samples.

Post Copper CMP Hybrid Clean Process for Advanced BEOL Technology

A “hybrid” post Cu CMP cleaning process that combines acidic and basic clean in sequence is developed and implemented. The new process demonstrates the strengths of both acidic and basic cleans and achieves a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. It also eliminates the circular ring defects that occur intermittently during roller brush cleans. TXRF scans confirm the reduction of AlOx defects when using the hybrid clean process. XPS spectra show similar Cu surface oxidation states between the basic and hybrid clean processes. As revealed by XRD analysis, surface Cu oxide is dissolved into aqueous solution by the acidic clean chemical. The formation mechanism of circular ring defects and the key to their elimination is discussed.

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

Optimization of post Cu CMP cleaning performance can be accomplished through dilution ratio tuning and pad rinse of clean chemicals. Excessive chemical etching as well as megasonic power can induce high Cu roughness. Generation of hollow metal and Cu dendrite defects depends not only on the clean chemistry but also the queue time between plating and anneal and between CMP and cap. AFM and XPS provide insights into the cleaning mechanism. EM and TDDB tests are the ultimate tests for the effectiveness of post Cu CMP cleaning.

Hybrid clean approach for post-copper CMP defect reduction

A “hybrid” post-Cu CMP cleaning process that combines acidic and basic cleans in sequence is developed and implemented. The new process demonstrates the advantages of both acidic and basic cleans and achieves a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic brush clean process. It also eliminates the circular ring defects that occur intermittently during roller brush clean. TXRF scans confirm the reduction of AlOx defects when using the hybrid clean process. XPS spectra show similar Cu surface oxidation states between the basic and hybrid clean processes. Both short and open yields can be improved by using the new clean process. The underlying mechanism of the huge defect reduction benefits is discussed.

Microreplicated pad conditioner for copper and copper barrier CMP applications

Metal-free micro-replicated conditioning disks are applied to the development of Cu and Cu barrier CMP processes for 22nm technology nodes. Compared with traditional pad conditioners with diamond grits embedded in metal matrix, the micro-replicated conditioners demonstrate lower within-wafer non-uniformity, more stable end-point time, more uniform and controllable pad wear, lower defectivity, and longer pad life time. Used pad analyses provide insights into the effectiveness of conditioning and guidelines for further process improvement.

Understanding, modeling, and detecting pooling hotspots in copper CMP

Multi-step Chemical Mechanical Polishing (CMP) has been used in copper interconnect fabrication for more than a decade. During this time, advances in both the CMP-based damascene manufacturing processes and in the design flows, have enabled significant uniformity improvements for both metal thickness and surface topography, producing corresponding improvements in parametric and functional yields and enabling smaller process nodes. However, improving post CMP planarity and widening CMP process windows have lead to an increased risk of functional yield failures due to copper pooling (sometimes called puddling). These failures occur when the overburden copper and/or barrier material is not cleared during CMP, producing an electrical short between two neighboring lines. We first sought to understand the source of this failure mode, based on recently reported research and data trends seen in state of the art copper CMP manufacturing processes. Once copper pooling mechanisms were identified, CMP models were enhanced to more accurately predict pooling hotspot locations. These models can be used to improve CMP process optimization and/or Design for Manufacturing (DFM) based flows that detect and remove pooling hotspots.

Planarization Specification for 22nm and Beyond BEOL CMP

This study discusses topography specifications for 22 nm and beyond CMP process and presents recent experimental data. We evaluated local topography impact on CD development in the subsequent layer using specially designed 22-nm test patterns. A wide range of localized erosions were generated in CMP within a single exposure field to avoid any focus-correction effect by the scanner or any other scanner-induced focus change between different levels of local erosion. Local erosions were measured by atomic force microscopy (AFM) after each process step from CMP to lithography to identify the local planarization effect from other film coatings between CMP and lithography. Post-litho CD inspection was done in the subsequent layer over the local erosion areas. Using experimental results, the paper also discusses BEOL pattern design rule for maximizing the process window.

Cu CMP Edge Uniformity Improvement Studies for 32 nm Technology Node and Beyond

Studies of the wafer edge uniformity step by step, from hard mask deposition, reactive ion etch, electroplating to post Cu CMP had been done using scanning electron microscopy (SEM) measurements, showed that the major wafer non-uniformity comes from the Cu CMP step. Improvement of Cu CMP edge uniformity had been achieved through engineering of platen 1 using real time profile control as well as CMP head zone pressure adjustment and platen 3 slurry optimizations

Evaluation of the Chemical-mechanical Planarization (CMP) Performance of Silicon Nitride and Silicon Carbide as Hard Mask Materials for Cu-based Interconnect Technology

Hydrogenated silicon nitride, hydrogenated silicon carbide, and their intermediates were chemo-mechanically polished. Results showed that, within the material set examined, harder materials also have higher CMP removal rates. In addition, CMP rates for multilayer stacks did not follow those for single layers. Polish mechanisms were proposed to explain these phenomena.

A BEOL multilevel structure with ultra low-k materials (k ≤ 2.4)

A multilevel back-end-of-line structure with a dielectric constant k ≤ 2.4 ultra low-k materials was developed. k=3D2.2 ULK build was demonstrated at a 144nm wiring pitch and a k=3D2.4 ULK was demonstrated at a 288nm pitch. Good model-to-hardware correlation for the measured capacitance indicated no significant plasma damage to the ULK 2.2 material. The extracted copper resisitivity was consistent with size-effect predictions of an electron scattering model. An optimized SiN/SiCxNyH bilayer copper cap scheme was developed to minimize low-k damage. Also, an alternative CoWP metal cap, for improved electromigration resistance, is discussed. Preliminary TDDB reliability testing suggests Vbd of ULK 2.2 144nm pitch structures and ULK 2.4 288nm pitch structures was comparable to that of dense low-k films at similar pitches, with very few extrinsic fails.