Laertis Economikos

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Plasma immersion ion implantation as an alternative deep trench buried-plate doping technology

Plasma immersion ion implantation (PIII) has been developed as an alternative deep trench capacitor buried-plate doping technology and compared to a conventional solid-state diffusion technique using arsenosilicate glass (ASG). Novel top-down (or vertical) SIMS measurements demonstrated the conformal doping capability of PIII along the trench sidewall. The doping level by PIII was almost one order of magnitude higher than that by a conventional technique. As a consequence, PIII provided better depletion characteristics than conventional technique. Furthermore, PIII processing did not degrade node-to-buried plate leakage current characteristics. From these results, it was demonstrated that PIII is a promising technology as an alternative deep trench capacitor buried-plate doping technique for future deep trench-based DRAM processing development.

Enabling Scatterometry as an In-Line Measurement Technique for 32 nm BEOL Application

Conventional metrology tools are unable to precisely monitor some interconnect attributes such as trench sidewall angle either due to limited capability or excessive cycle time. But these attributes have great impact on interconnect performance for 32 nm technology node and beyond. Scatterometry, a non-destructive metrology technique, is proposed to address the shortcomings of current metrology tools while also potentially providing additional measurement capabilities that enable more comprehensive characterization of interconnect attributes. Enabling scatterometry for back-end-of-line metrology at 32 nm technology node is challenged by the inherent complexity of a multilayer film structure. The research reported describes the implementation of scatterometry measurements to explore the advantages of this technique for the 32 nm technology node. The results obtained demonstrate the superiority of scatterometry techniques over conventional semiconductor metrology tools such as throughput, process control capability, precision, and accuracy. The total measurement uncertainty of scatterometry results with tunneling electron microscope and cross-sectional scanning electron microscope results for line height shows 1.92 and 6.46 nm, respectively, which compare favorably to the reference metrology tools. Scatterometry techniques also exhibited impressive potential to estimate end-of-the-line electrical parametric data. Finally, physical dimensions obtained from scatterometry measurements are shown to be comparable to TEM results from product wafers.

Computer vision for automatic inspection of complex metal patterns on multichip modules (MCM-D)

Computer vision techniques have been developed and implemented in a high volume manufacturing environment for automatic optical inspection (AOI) of multichip modules with thin films (MCM-D). Inspection-of complex thin film metal patterns for critical defects despite high topological and cosmetic variation is discussed in this paper. An Orbot TF501 inspection platform was used to implement the procedures and algorithms. The techniques presented are capable of detecting both electrical and non-electrical defects. Electrical defects include near shorts, resistive opens, and near opens such as dishdowns where there may be a local height reduction in a signal line. Non-electrical defects include wrong metallurgy, defects with height and contamination. AOI may be used to shorten cycle time, improve yields and better control latent defects. >

Open repair technologies for MCM-D

IBM has developed various technologies for repairing defects in thin film circuitry, primarily for Multichip Module (MCM) applications. This paper discusses five technologies: laser chemical vapor deposition (LCVD), wire bond, laser-sonic bonding, solder repair, and self-induced repair, with focus on the process parameters and tooling aspects of the three established in IBMs production environment. >

Post Copper CMP Hybrid Clean Process for Advanced BEOL Technology

A “hybrid” post Cu CMP cleaning process that combines acidic and basic clean in sequence is developed and implemented. The new process demonstrates the strengths of both acidic and basic cleans and achieves a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. It also eliminates the circular ring defects that occur intermittently during roller brush cleans. TXRF scans confirm the reduction of AlOx defects when using the hybrid clean process. XPS spectra show similar Cu surface oxidation states between the basic and hybrid clean processes. As revealed by XRD analysis, surface Cu oxide is dissolved into aqueous solution by the acidic clean chemical. The formation mechanism of circular ring defects and the key to their elimination is discussed.

Hotspot detection and design recommendation using silicon calibrated CMP model

Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for todays designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

Optimization of post Cu CMP cleaning performance can be accomplished through dilution ratio tuning and pad rinse of clean chemicals. Excessive chemical etching as well as megasonic power can induce high Cu roughness. Generation of hollow metal and Cu dendrite defects depends not only on the clean chemistry but also the queue time between plating and anneal and between CMP and cap. AFM and XPS provide insights into the cleaning mechanism. EM and TDDB tests are the ultimate tests for the effectiveness of post Cu CMP cleaning.

Fixed Abrasive Technology for STI CMP on a Web Format Tool

Shallow trench isolation (STI) requires a high quality oxide with superior fill capability provided by High Density Plasma (HDP) oxide. Unfortunately, the HDP deposition process can create large within die topographies that are difficult to polish directly using conventional silica slurries. As a result, etch back integration schemes have traditionally been incorporated for STI polish. A more revolutionary approach is the use of Fixed Abrasive (FA) CMP [1]. FA CMP allows direct STI polish with good planarization/process stability, eliminating the need for prior etch back. The planarization efficiency is strongly dependent on the shape of the pad composites that hold the CeO 2 mineral. Fixed abrasive pads with pyramid and pole shapes are available. In this work, three different fixed abrasive pads supplied by 3M corporation were evaluated for STI CMP polish performance using the Obsidian 8200C web format CMP tool. Basic polish characteristics such as planarity (dependence on sub-pad/pattern density), selectivity to topography, oxide dishing and nitride erosion are presented. The FA pads discussed here have been classified as “slow”, “medium” or “fast” depending on blanket oxide removal rate. The slow rate pad had a very high selectivity to topography and very low dishing of the down area oxide. The removal rate of blanket oxide was less than 100 A/min. The pad was best suited to the polish of isolation trench structures with small, controlled overfill (> 200 A) across the wafer. A large process window was demonstrated. The removal rate of the “medium” pad also decreased significantly at the onset of planarization with a blanket oxide removal rate of ca. 200 A/min. Unlike the slow rate pad, the medium rate pad did not provide a suitable overpolish process window required for a manufacturable STI process. It is believed this pad would be a good choice for BPSG polish. In contrast to the slow and medium rate pads, the blanket oxide removal rate of the fast pad was ca. 2000 A/min with no self-stopping capability at the onset of planarization. The removal rate was extremely center fast, such that it could not be compensated by adjustment of tool parameters. Use of a modified process developed within the DRAM development alliance (DDA) at East Fishkill (IBM/ Infineon) enabled the fast pad to polish deep STI structures that would otherwise be impossible using the slow or medium rate pads.

Technologies for scaling vertical transistor DRAM cells to 70 nm

Vertical transistor DRAM cells have been demonstrated as viable in the 110 nm generation. This paper describes the issues associated with scaling these cells to the 70 nm node and demonstrates fixes to all known issues. Scaling to 70 nm is possible through the development of two key enabling technologies, high aspect ratio STI fill and low resistance metal deep trench fill, and through minor cell modification. Each of these items are addressed and shown to be viable using a functional 512 Mb prototype DRAM chip at 110 nm half-pitch groundrule. Based on these results, we believe the vertical transistor DRAM cell is one of the most promising for continued scaling of conventional DRAM and embedded DRAM cells.