Shea Jue Wang

Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

Abstract Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

Electrical performance of a-Si:H and poly-Si TFTs with heating stress

The amorphous channel (a-Si:H) TFT-LCD technology dominates the large-area flat panel display (FPD) market, but a-Si:H TFTs propose some adverse characteristics, especially in mobility. Therefore, developing poly-Si TFTs to promote mobility and implement the chip-on-glass (CoG) dream is indeed necessary. Using a green continuous-wave laser on amorphous silicon channel formed as poly-crystallization is a possible way in increasing the mobility value up to 450 cm2/V·sec. However, the electrical characteristics for them face the identical trend with temperature heating is degraded. However, the degradation of a-Si:H TFT is worse than that of poly-Si TFT when the device temperature is raised. In this study, the a-Si:H TFTs and poly-Si TFTs with furnace and green laser anneal were chosen. Comparing the transfer characteristics, subthreshold swing (S.S.), threshold voltage (Vth), ON/OFF ratio, field effect mobility (μFE), interface state density (Nit) with temperature effect, some trends are very interesting. The bulk traps were recovered by pseudo-crystallization with increasing temperature, and the transfer characteristics become better than the initial.

Trend of subthreshold swing with DPN process for 28nm N/PMOSFETs

Although decoupled plasma nitridation (DPN) post high-k dielectric deposition shows the better threshold voltage shift than post deposition anneal (PDA), the non-adequate plasma nitrogen (N) concentration and anneal temperature still can dominate the device performance. Using these two variables to probe the impact of HK deposition integrity and the interface quality between channel and gate dielectric is an undetected and published topic. In the experiment, the lower N-concentration and higher anneal temperature is beneficial to the higher drive current and lower threshold for NMOSFET. However, the PMOSFET prefers the lower anneal temperature as well as lower N-concentration. Additionally, the phenomena for the combination of DPN process and strain engineering causing the non-uniform trend distribution of subthreshold swing with device channel lengths were exposed.

Punch-through and junction breakdown characteristics for uniaxial strained nano-node metal-oxide-semiconductor field-effect transistors on (100) wafers

In the nano-regime MOSFET devices, the punch-through effect is more distinct, retarding the reliability tolerance, such as electro-static discharge or latch-up applications. Through the measurement in various device lengths under contact-etch-stop-layer strain process or without strain effect for 45 nm complementary MOS process, the difference of punch-through effect and junction breakdown integrity were able to be classified and exhibited in design applications. After tested data analysis, the junction breakdown issue in PMOSFET was usually greater than that in NMOSFET due to the doping concentrations and the doping species. Generally, the junction breakdown value is independent of channel length variation except the existence of some damage close to the gate/source or gate/drain fringe. In addition, the punch-through voltage for PMOSFET as source/drain current IDS = 1 μA is also larger than that observed for NMOSFET.

High Quality of 0.18μm CMOS 5.2GHz cascode LNA for RFID tag applications

An operation in 1.8V supply voltage single-ended cascode low-noise amplifier (LNA) structure was launched. This designed circuit provided the lower noise figure and matched the suitable LC tank to enhance the central operating frequency as well as the excellent input and output impedance matching incorporated into this LNA circuit. In this simulation, the Agilent ADS (Advanced Design System) simulation software and tsmc 0.18 μm CMOS process parameters were adopted to achieve the low-cost characteristics and high integration to fit the performance of 5.2 GHz LNA design under IEEE 802.11a specification. Due to the precise calculation gaining the good impedance matching, the simulation results showed the forward gain (S21) about 12.96dB, as well as less than -15dB isolation (S12). The input impedance (S11) and the output impedance (S22) also represented good performance. In addition, the minimum noise figure and the signal linearity performance were quite good, so that this LNA circuit was better in the availability and possibility of RFID tags.

Kink effect for 28 nm n–channel field–effect transistors after decoupled plasma nitridation treatment with annealing temperatures

The kink effect of drain leakage based on gated diode measurement metrology for the tested nMOSFETs with 28 nm HK/MG, gate–last and PDA or DPN nitridation processes was observed at VG around −0.6 V when the gate voltage was swept from −Vcc to 0.2 volt as VD = 0.1 V. Nevertheless, this interesting phenomenon was not evident as the gate voltage was reversely swept from 0.2 volt to -Vcc. The chief mechanism in speculation can be illustrated by the electrons coming from drain inducing capture–and–emission behaviour by the channel interface traps near the drain junction. While VG changes from −Vcc towards +0.2 V, interface states near valence band become lower than Fermi–level of silicon substrate. Electrons flow from drain to fill these interface states so that drive current (ID) increases. On the contrary, as VG changes from +0.2 V to −Vcc, the trapped electrons are recombined with holes from substrate so that ID is not affected. This kink effect for all of tested devices is not very distinct far and near. When the Poole–Frenkel (P–F) tunnelling electrons coming from gate to drain are evident in leakage, especially at the long–channel device, this effect will be probably counteracted, exhibited at the electrical characteristics of PDA group.

Characteristics and hot-carrier effects of strained pMOSFETs with SiGe channel and embedded SiGe source/drain stressors

The embedded SiGe source/drain stressor helpful to promote the drive current involves etching out the source/drain silicon and replacing it with SiGe filler. This process uses the lattice mismatch between silicon and germanium atoms making the silicon channel compressive. This compressive stress enhances hole mobility, and the pMOSFET performance can be enhanced. In this study, the characteristics of devices contained biaxial strain in channel and embedded SiGe source/drain stressor with different channel lengths and the channel hot carrier (CHC) in short channel pMOSFETs was explored, too.

Probing moving charge distribution of biaxial and CESL strained PMOSFETs with body effect

Using body effect to probe the inversion charge distribution is a feasible method in qualitative analysis, especially for sandwich embedded SiGe structure in nano-node semiconductor strained engineering. In this study, there were three tested (100) wafers with non-strained, compressive strained and tensile strained types. After analysis, no matter what the compressive or the tensile was, the inversion current flow for PMOSFETs mainly located in biaxial strained SiGe channel due to N-well bias. The related electrical characterizations with well biases were also exhibited.

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (VT) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

Body effect of SiGe and CESL strained nano-node NMOSFETs on (100) silicon substrate

An alternative technique to improve the electric performance of shrunk MOSFET devices is strained engineering. Considering SiGe channel layer as a global strain capping a Si layer to prevent Ge diffusion from the SiGe channel layer and soften the stress between SiON gate dielectric and SiGe channel is a possible way. To favor NMOSFET, depositing silicon nitride on gate as contact etching stop layer (CESL) process providing the tensile effect is more appreciated. In this study, besides the electrical characteristics with different strain processes, the conduction path and channel location of electron carrier through body bias adjustment is an attractive exploration. Because the charge profile in channel shown as a quantum mechanical effect is not a uniform distribution, the chief inversion layer thickness of electron carrier will be shifted when the substrate bias is applied. This evidence will be exhibited in gamma factor. Observing the gamma shift, the main conductive path of electron carrier can be diagnosed and analyzed about the quality of SiGe layer in growth.