Mu-Chun Wang

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Interface trap generation and recovery mechanisms during and after positive bias stress in metal-oxide-semiconductor structures

Interface trap (Nit) generation and their partial recovery during and after cessation of the positive bias-temperature stress (PBTS) in n-type metal-oxide-semiconductor capacitors have been investigated. The analysis of experimental results indicates that Nit creation is caused by the depassivation of Si3≡Si-H bonds at the Si/SiO2 interface by the atomic neutral hydrogen (H0) cracked via electron impact at or near gate/oxide interface during electron injection from the substrate. Nit recovery after interruption of the stress is due to back diffusion of H2 species toward the Si/SiO2 interface and repassivation of Si3≡Si• dangling bonds. We propose that in absence of holes, a modified one dimensional reaction-diffusion (R-D) model following three step degradation sequences can qualitatively explain the generation and the recovery of Nit during and after PBTS.

The Instability of a-Si : H TFT under Mechanical Strain with High Frequency ac Bias Stress

The instability of amorphous Si thin film transistors under uniaxial strain has been studied. Compared to the effect of tensile bias stress, larger threshold voltage shift is observed under compressive bias stress. These results are related to the damage of weak Si-Si bonds during the ac bias stress. However, the V th shift of devices on the re-flattened substrate is larger after tensile strain than that of compressive strain. In addition, the defeat diminished effect of tensile situation is decreased after re-flattening the device. Therefore, after re-flattening the substrate the V th shift resulting from tensile bias stress is larger than that of the compressive one.

Visible Light Source Disturbing the Source/Drain Current of CLC Poly-Si n-TFT Device

CLC Poly-Si n-TFT Device M.C. Wang, Z.Y. Hsieh, C. Chen, J.M. Shieh, Y.T. Lin, H.S. Huang Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, 10601, Taiwan Department of Material Science & Engineering, National Chiao Tung University, Hsinchu 300, Taiwan National Nano Device Laboratories, Hsinchu 30078, Taiwan *Dept. of Electronic Engineering, Ming-Hsin University of Science and Technology; No. 1 Hsin-Hsing Road, Hsin-Fong, Hsin-Chu, 304, Taiwan; e-mail: mucwang@must.edu.tw.

Drive current and hot carrier reliability improvements of high-aspect-ratio n-channel fin-shaped field effect transistor with high-tensile contact etching stop layer

A high-aspect-ratio 3D multi-gate n-channel fin-shaped field effect transistor (FinFET) has been integrated with a stressor of a highly tensile nitride film as the initial inter layer dielectric capping layer upon a (110)-orientated silicon-on-insulator wafer. Drastically enhanced electrical performances, such as 190% enhancement of peak channel mobility, 91% of peak transconductance, and 34% of saturation current, etc., are achieved for an NMOS FinFET with a gate length of 90 nm. The Ioff-Ion universal curve also demonstrates an extraordinary drive current gain of 26%. Moreover, the hot carrier injection lifetime can be increased from 7.78 × 102 to 5.26 × 103 year (yr) due to the incorporation of this high-tensile contact etching stop layer and relaxation of the Si crystalline channel layer.

Suppression of Schottky leakage current in island-in amorphous silicon thin film transistors with the Cu∕CuMg as source/drain metal

The feasibility of using Cu∕CuMg as a source/drain metal for the island-in amorphous silicon thin film transistors (a-Si:H TFTs) has been investigated. The issue of adhesion between the Cu film and n+–a-Si layer has been overcome by introducing the Cu∕CuMg alloy. Furthermore, the suppression of Schottky leakage current in metal/a-Si:H structure was also observed in the island-in a-Si:H TFT. The island-in a-Si:H TFT exhibited the mobility of 0.52cm2∕Vs, the subthreshold slope of 0.78V∕decade, and the Vth of 3.02V. The experimental result also showed superior performance of the a-Si:H TFT with minimal loss of critical dimension and good thermal stability.

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicided CMOS process

Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996).

Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process

An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS ICs is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-/spl mu/m shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS ICs, but still to maintain high enough latchup immunity in bulk CMOS ICs.

Gate Leakage Characteristics for 28 nm HfZrO x pMOSFETs After DPN Process Treatment With Different Nitrogen Concentration

Feasibly adjusting the gate leakage and the device performance in balance is an obvious challenge. Additionally, stacking the high-k dielectric as a gate dielectric in nanonode process is an appreciate way to promote the drive current in pMOSFETs. Unfortunately, the amount of oxygen vacancy or the interfacial layer thickness on the surface channel will possibly reduce the drive current owing to the increasing magnitude of threshold voltage and increase in the gate leakage degrading the standby capability in circuit operation. To retard this disadvantage or intensify the device quality, applying a lower pressure decoupled-plasma nitridation process to obliquely reform the amount of oxygen vacancy is a feasible alternative. On the basis of tested data, the nitridation treatment in a higher N2 concentration is better than that in a lower one, such as the improvement of gate leakage, drive current, subthreshold swing, and channel mobility in pMOSFETs, especially for shorter channel-length devices.

Analysis of promising copper wire bonding in assembly consideration

Although gold wire proposes the good characteristics such as malleability and stabilization, in the cost consideration to promote the package competition, the copper wire provides the better attraction. Therefore, the assembly houses gradually impress on the copper wire bonding technology desirably replacing the traditional gold wire bonding, especially in high-pin-count package. Besides the cost superiority, the electrical resistivity of copper, 1.7 µΩ-cm, is lower than that of gold, 2.2 µΩ-cm, and aluminum, 2.65 µΩ-cm. Furthermore, the mechanical characteristics of copper, such as Youngs modulus and rigidity modulus (130 GPa and 48 GPa, respectively), are larger than those of gold (78 GPa and 27 GPa, respectively). In copper wire bonding, the wire ball on pad demonstrates the excellent neck intensity and the arc shape of the copper wire is more stable. This superiority in molding process is singularly and significantly noticeable.