Hsin-Chia Yang

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Promising 6.0-12 GHz Low Noise Amplifiers by Combining Two Matched Amplifiers

Devices fabricated and modeled through TSMC 0.18 micron CMOS processes are used to design radio frequency amplifiers. Two different mechanisms are applied to produce low noise amplifiers (LNA) and Class-E power amplifiers (PA) at various center working frequencies. Both amplifiers at the same working frequency are thus put together to enhance the gain. The enhancement can be easily done because they are impedance-matched prior to the combination. Noise figures are always suppressed because LNA component is intentionally put ahead of PA component. Both components are integrated into one large component. This integrated component has the features of low noise figure and high power added efficiency. The linearity and the interference is to be shown. In this paper, the forward gain at 6.0 GHz center working frequency achieves 55.148 dB just as expected. Its magnitudes of both S11 and S22 in the Smith Chart do approach to zero. And its Noise Figure is as low as 1.175. A promising integrated circuit is then to be found. Using the same algorithm, one can also show other optional possibilities at different center working frequencies.

Electrical performance of a-Si:H and poly-Si TFTs with heating stress

The amorphous channel (a-Si:H) TFT-LCD technology dominates the large-area flat panel display (FPD) market, but a-Si:H TFTs propose some adverse characteristics, especially in mobility. Therefore, developing poly-Si TFTs to promote mobility and implement the chip-on-glass (CoG) dream is indeed necessary. Using a green continuous-wave laser on amorphous silicon channel formed as poly-crystallization is a possible way in increasing the mobility value up to 450 cm2/V·sec. However, the electrical characteristics for them face the identical trend with temperature heating is degraded. However, the degradation of a-Si:H TFT is worse than that of poly-Si TFT when the device temperature is raised. In this study, the a-Si:H TFTs and poly-Si TFTs with furnace and green laser anneal were chosen. Comparing the transfer characteristics, subthreshold swing (S.S.), threshold voltage (Vth), ON/OFF ratio, field effect mobility (μFE), interface state density (Nit) with temperature effect, some trends are very interesting. The bulk traps were recovered by pseudo-crystallization with increasing temperature, and the transfer characteristics become better than the initial.

Low Effective SiO2 Thickness and Low Leakage Current Ta2O5 Capacitors Based on Tantalum Tetraethoxide Dimethylamino-Ethoxide Precursor

Tantalum pentoxide (Ta2O5) films have been chemically deposited at low pressure on heavily phosphorous doped poly silicon using oxygen and a metal organic precursor, tantalum tetraethoxide dimethylamino-ethoxide Ta(OC2H5)4(OC2H4N(CH3)2), (TATDMAE). Good conformality of Ta2O5 films was seen. Hydrocarbon contamination was reduced by way of the annealing processes. The capacitance and the leakage current of the patterned capacitors were measured. Continuous improvements based on the crystallization and the reduction of hydrocarbon contamination were achieved by reducing the effective SiO2 thickness (teff, or the equivalent SiO2 thickness), and teff~30.6 A on average was achieved for 100-A-thick Ta2O5 films. Crystallization occurs at 800°C or above upon application of rapid thermal processing (RTP) in the N2 ambient. During crystallization, hydrocarbon contaminations are out-diffused, which leaves dangling bonds in the as-deposited Ta2O5 films. To reduce the dangling bonds, the films were continuously processed by means of RTP in an O2 or N2O ambient. The leakage current was measured and plotted. The I–V plot shows the non-symmetric structure, namely metal–insulator–silicon (MIS), and the leakage current at 1.0 V achieves 1.190×10-9 A/cm2.

Nano-scale Si-capping thicknesses impacting junction performance on silicon substrate

Silicon capping layer is a useful dielectric smoothing the interface integrity between gate dielectric and SiGe deposition layer in nano-scale process technology and reducing the possibility of Ge atom diffusion into the gate dielectric. However, the junction performance in reverse saturation current is suffered. Through the deliberate pattern design, the fringe junction leakage for MOSFET device was effectively extracted. The thicker Si capping layer well prevents Ge atom from diffusing into gate dielectric, but causes more fringe junction leakage at source/drain sites.

Minimization of Cascade Low-Noise Amplifier with 0.18 μm CMOS Process for 2.4 GHz RFID Applications

The cascade LNA circuit adding parasitic capacitance (Cp) for neighboring passive inductors at 2.4GHz with low-cost and high-integration 0.18μm CMOS process was designed and studied. The simulation results adopting an ADS software as a simulator demonstrated the forward voltage gain is 11.908dB, the input return loss is -9.563dB, the output return loss is -21.153dB, the reverse isolation is -16.315dB, the minimum noise figure is 2.01dB and the 3-dB gain bandwidth is 240MHz. Comparing the performance with Cp and without Cp, we observed that they indeed had some change. The noise figure was slightly reduced and the voltage gain was increased a little. The benefit of chip size shrinkage was about 3%. Totally, these interesting parameters still verify that this contrived LNA with ultra-low noise performance plus parasitic capacitance effect is still suitable to be a candidate in the whole receiver integration for RFID applications.

CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication

In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This phenomenon is obviously observed with devices, width/length=W/L= 10/10 and 10/.08 (µm/µm). Moreover, the trend evidence for tensile strain benefited to nMOSFETs and pMOSFETs, but for compressive strain favoring pMOSFTEs and not hugely degrading nMOSFETs, is also achieved.

A study to performance of electroplating solder bump in assembly

The electroplating methodology in assembly is better than the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging), especially in quality. Through eight-step process requiring one photolithographic mask, the pre-WLCSP procedures for the electroplating solder bump technology are able to be completed. Comparing this technology with the electroplating gold bump technology, the cost in the previous is more impressive even though the performance of this technology is little lower than the last. Therefore, in this study, the electroplating solder bump in assembly was probed in detail to analyze the possibility of mass-production.

Determination of capacitance of DRAM capacitor as encountering roll-off problems

There has been trouble in measuring larger-area DRAM capacitors, especially at higher frequency. Somehow, different area size capacitors are supposed to have the same capacitance per unit area due to the reliable and repeatable process technology. A model using an algorithm based on Metal- Insulator-Semiconductor (MIS) structure is to be developed to understand the reasons why roll-off problems of measurements take place as the frequency gets higher and the areas of capacitors get larger. It is then found that the common unit capacitance C0, 1.1255E-5 nF/μm, of various size capacitors with 100Å Ta2O5 dielectric corresponds to the effective SiO2 thickness, 30.5 Å.

Punch-through and junction breakdown characteristics for uniaxial strained nano-node metal-oxide-semiconductor field-effect transistors on (100) wafers

In the nano-regime MOSFET devices, the punch-through effect is more distinct, retarding the reliability tolerance, such as electro-static discharge or latch-up applications. Through the measurement in various device lengths under contact-etch-stop-layer strain process or without strain effect for 45 nm complementary MOS process, the difference of punch-through effect and junction breakdown integrity were able to be classified and exhibited in design applications. After tested data analysis, the junction breakdown issue in PMOSFET was usually greater than that in NMOSFET due to the doping concentrations and the doping species. Generally, the junction breakdown value is independent of channel length variation except the existence of some damage close to the gate/source or gate/drain fringe. In addition, the punch-through voltage for PMOSFET as source/drain current IDS = 1 μA is also larger than that observed for NMOSFET.