Wen-Ta Lee

Hysteresis-Current-Controlled Buck Converter Suitable for Li-Ion Battery Charger

A new hysteresis-current-controlled (HCC) buck converter suitable for Li-ion battery charger is presented in this paper. The technique adopted in this charger is constant current/constant voltage dual mode, which is decided by the value of internal resistance of Li-ion battery. This technique will degrade the damage of Li-ion battery and improve the power efficiency of charger. The Li-ion battery charger is designed with 0.35 - mum CMOS DPQM processes. The simulation results show that the charger works well and confirms with theoretical analysis. The power efficiency of charger can be up to 82% under the average power of 825 mW. The chip area is only 1.71times 1.52 mm 2.

New power saving design method for CMOS flash ADC

A new power saving design method for CMOS flash ADC is presented. With an inverter as a comparator along with an NMOS and a PMOS as switches, we use bisection method to let only half of comparators in flash ADC working in every clock cycle. An example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in power consumption.

A multi-mode LDO-based Li-ion battery charger in 0.35/spl mu/m CMOS technology

The paper designs a CMOS Li-ion battery charger that uses multi-mode low dropout (LDO) voltage regulator associated with current sense circuit to supply trickle current, large constant current and constant voltage. The whole circuits have been approved by HSPICE with TSMC 0.35/spl mu/m 2P4M CMOS process. The simulation results provide the trickle current of 150mA, the maximum charging current of 312mA and charging voltage of 4.2V at input voltage of 4.5V. The power efficiency of 72.3% is acceptable under the power of 1.28 W.

A high precision ramp generator for low cost ADC test

In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output resistance (Ro) and then get the smaller integral nonlinearity (INL) error. Eventually, we have designed a ramp generator chip using TSMC CMOS 0.35 ¿m 2P4M technology. The core area without I/O pad is 144 ¿m × 277 ¿m, operation voltage is 3.3 V. Experimental results show that the chip has a ramp signal of 2 V full range with duration of 100 ¿S and measured a maximum INL of 20 ¿V only. The linearity of the ramp waveform equals to 16 bits resolution. Such linearity allows the test of ADC up to 14 bits.

A new low-power turbo decoder using HDA-DHDD stopping iteration

In this paper, we present a new VLSI architecture for a low-power turbo decoder. First, we develop a new soft-in-soft-out decoder architecture and change the sliding window operating flow without attaching LIFO memory. Moreover, we propose a new stopping iteration algorithm that integrates two stop criteria to avoid unnecessary iterations, especially in low SNR channels. Experiments show that our architecture gets 25.3%/spl sim/39.8% memory size saving in our SISO decoder architecture and one window saving of decoding delay in comparison with the traditional decoder.

An embedded analog spatial filter design of the current-mode CMOS image sensor

This investigation presents an embedded analog spatial filter, EASF, in a current-mode CMOS image sensor. The EASF successfully identifies the output value of the pixel in B/W so as to benefit specific real world applications. Over the last few years, image quality has been improved by better progress in CMOS process technology; however, low cost issue regarding the integration of backend circuit still is an important competition point in imager design. Embedding an analog mask filter in a CMOS image sensor not only reduces cost, but also improves speed and simplicity of design integration with the backend image processing circuit. In this paper, a 66 x 66 embedded sensor array has been implemented in TSMC 0.35 /spl mu/m CMOS process. Each pixel occupies a 13.8 /spl mu/m x 9.8 /spl mu/m area with a fill factor of 31.2%. The power consumption is 71.14 mW when the sensor operates at 32 frames/sec.

A New Low Power Flash ADC Using Multiple-Selection Method

This paper presents new low power CMOS flash analog-to-digital converter (ADC) using multiple-selection method. As an example of 6-bit flash ADC, we use three extra comparators in our design to divide the next stage into four sections and control the switches whether can proceed to the 4-bit modified flash ADC or not. We use multiple-selection method to let only one section of the 4-bit modified flash ADC is allowed to operate, which achieve the aim of the low power consumption. Simulation and experimental results show that this proposed 6-bit flash ADC consumes about 19.2 mW at 800 M sample/s with 3.3 V supply voltage in TSMC 0.35 mum 2P4M process. Compared with the traditional flash ADC, this multiple-selection method can reduce about 80.3% in power consumption.

A new CCII-based pipelined analog to digital converter

This paper proposes a new pipelined analog to digital converter (ADC) based on second-generation current conveyors (CCII). Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifiers (OA). Simulation results show that the proposed CCII-based pipelined ADC can work at 10 MHz with an 8-bit resolution. The DNL is within -0.4 LSB and 0.5 LSB and INL is within -0.4 LSB and 0.7 LSB, respectively. The ADC is realized in TSMC 0.35 /spl mu/m CMOS technology and consumed 29 mW under a 3.3 V power supply. The core size is 0.85/spl times/0.85 mm/sup 2/.

High-order linear transformation MOSFET-C filters using operational transresistance amplifiers

High-order linear transformation (LT) MOSFET-C filters using operational transresistance amplifiers (OTRA) are presented in this paper. The systematic method is developed to realize LT OTRA-based filters efficiently. Based on the proposed design procedures, we can synthesize high-order filters with OTRA along with MOSFET resistor circuits (MRC) and capacitors. A third-order Chebychev lowpass filter is demonstrated. Experimental results that confirm the theoretical analysis are obtained. Furthermore, the proposed circuits can be extended to higher-order filters.

Versatile universal voltage-mode filter employing minimum components

A novel versatile single FDCCII-based voltage-mode universal biquadratic filter with three inputs and four outputs is presented. The proposed circuit can act as a multifunction voltage-mode filter with two inputs and four outputs and can perform simultaneous realization of voltage-mode bandreject, highpass, bandpass and lowpass filter signals from the four output terminals, respectively. On the other hand, it also can act as a universal voltage-mode filter with three inputs and a single output and can realize five generic voltage-mode filter signals without requiring any inverting input voltage signals and component-matching conditions. The proposed circuit employing single FDCCII, two grounded capacitors and two resistors, which are the minimum components necessary for realizing a second-order voltage-mode universal filtering response from the same topology. Both its active and passive sensitivities are low.