Wolfgang Heinrigs

Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements

We present a new direct VT measurement technique with arbitrary choice of drain voltage and a mus delay (factor of 1000 improvement) after stress. As shown this technique enables a meaningful comparison of data to theory (e.g. DeltaVT measurable as response to stress times from 100mus over 10 decades in time and an analysis of recovery over 11 decades in time) which may lead to a better understanding of NBTI. A fast precursor due to bulk trapping was found to significantly influence degradation slopes for all times. Based on a physical model - standard reaction/diffusion model plus fast bulk trapping -with just 3 fit parameters experimental degradation can be well modelled and degradation slopes <frac14 as well as > frac14 (both reported in literature) can be explained. A lifetime extrapolation based on this physical model is superior to the common straight line fit. There is no satisfying agreement of recovery data with reaction/diffusion theory. Further experimental and theoretical work is going to be needed

A Comparison of Very Fast to Very Slow Components in Degradation and Recovery Due to NBTI and Bulk Hole Trapping to Existing Physical Models

A new measuring technique with a 1mus measuring delay and a direct VT determination has been employed. The response to stress times as short as 100 mus to 105 has been studied as well as recovery over 12 decades in time. These experimental data allow a meaningful comparison to theory. Degradation data cut be precisely fitted to a simple physical model with 3 parameters thus enabling a reliable lifetime prediction from stress times below 104s.

On the impact of the NBTI recovery phenomenon on lifetime prediction of modern p-MOSFETs

The NBTI recovery phenomenon leads to a fast reduction of the stress induced electrical device parameter degradation after end of stress. Delay times between device-stress and -characterization within NBTI-experiments affect the measurement values of degradation. This work discusses the impact of these delays on lifetime prediction for technology qualifications. For this reason we investigate delay times from 1mus up to 60s and stress times from 100ms up to 250000s. A correlation between stress time, delay time induced recovery and error in predicted lifetime is elaborated for the first time. Furthermore we give simple guidelines for measurement requirements and essential stress times for accurate lifetime evaluations

A novel multi-point NBTI characterization methodology using Smart Intermediate Stress (SIS)

In recent literature several measurement methods were introduced to characterize the Vth-degradation due to NBTI considering the recovery phenomenon. To our knowledge each method has a severe problem or at least a significant disadvantage. Either there are long delay times, the accuracy is not satisfactory or it is not possible to implement the method with customary equipment. A compromise is to perform a one point measurement in the subthreshold region and calculate Vth based on the assumption that the subthreshold slope is not affected by NBTI. In this paper we disprove the universality of this assumption. Vth determination using a one point measurement can lead to imprecise values. This extraction method disregards changes of the subthreshold slope due to NBTI, however a change of the slope impacts the extracted Vth. We clearly demonstrate this effect with our measurements. We introduce a new smart Vth extraction methodology offering both shortest possible delay times with customary equipment and consideration of NBTI-impact on subthreshold slope.

Consideration of recovery effects during NBTI measurements for accurate lifetime predictions of state-of-the-art pMOSFETs

The NBTI recovery phenomenon leads to a fast reduction of the stress induced electrical device parameter degradation after end of stress. Delay times between device-stress and -characterization within NBTI-experiments affect the measurement values of degradation. This work discusses the impact of these delays on lifetime prediction for technology qualifications. For this reason we investigate delay times from 1mus up to 60s and stress times from 100ms up to 250000s. A correlation between stress time, delay time induced recovery and error in predicted lifetime is elaborated for the first time. The influence of the recovery on single device stress experiments, on the voltage acceleration and finally on lifetime extrapolation is discussed. Furthermore we give simple guidelines for measurement requirements and essential stress times for accurate lifetime evaluations.

A new smart V th -extraction methodology considering recovery and mobility degradation due to NBTI

In the recent literature several measurement methods were introduced to characterize the Vth-degradation of NBTI considering the recovery phenomenon. To our knowledge each method has a severe problem or at least a significant disadvantage. Either there are long delay times, the accuracy is not satisfactory or it is not possible to implement the method with customary equipment. A compromise is to do a one point measurement in the subthreshold region and calculate Vth based on the assumption that the subthreshold slope is not or only marginally affected by NBTI. In this paper we disprove the universality of this assumption. Vth determination using a one point measurement can lead to imprecise values. This extraction method disregards mobility degradation after NBTI impacting Vth, which we have clearly obtained in our measurements. We introduce a new smart Vth extraction methodology offering both shortest possible delay times with customary equipment and consideration of mobility degradation effects.

Hot-carrier induced dielectric breakdown (HCIDB) challenges of a new high performance LDMOS generation

A new generation of embedded-power technologies offering high performance LDMOSFETs was introduced and particularly the reliability of the devices were characterized. The combination of a 120nm logic process with LDMOS with thin gate oxide enables high efficiency power converters on small die sizes. The reliability of the new LDMOS transistors had to be optimized very accurately to achieve both reliable products and the new RON benchmark.