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Dive into the research topics where Wolfgang Roesner is active.

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Featured researches published by Wolfgang Roesner.


Semiconductor Science and Technology | 2006

Validation of 30 nm process simulation using 3D TCAD for FinFET devices

Muhammad Nawaz; Wolfgang Molzer; Patrick Haibach; Erhard Landgraf; Wolfgang Roesner; Martin Staedele; Hannes Luyken; Alp H. Gencer

This paper targets to show feasibility of a three-dimensional process simulation flow in the context of optimization of the device design and the underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm FinFET devices. The major goal of the simulation work is to implement a complete FinFET process flow into a commercially available 3D process simulation environment. Furthermore, all important three-dimensional geometrical features, such as corner roundings and 3D facets, have been introduced into the simulation set-up. After the successful demonstration of a functional 3D process simulation flow, detailed issues of process simulation methodology are assessed, such as the usage of different dopant diffusion models or the modelling of specific oxidation processes plus assessment of different annealing conditions. Finally, a comparison of the simulation results with electrical measurement data is performed which shows fairly good agreement.


international symposium on power semiconductor devices and ic's | 2015

Multi-dimensional trade-off considerations of the 750V micro pattern trench IGBT for electric drive train applications

Frank Wolter; Wolfgang Roesner; Maria Cotorogea; Thomas Geinzer; Martina Seider-schmidt; Kae-Horng Wang

The EDT2 750V uses a micro pattern trench cell with a narrow mesa for reducing the on-state losses with a tailored channel width for short circuit robustness. To account for high system stray inductances (Lstray) and currents for Full or Hybrid Electric Vehicle inverter applications, it features a 750V voltage rating compared to the predecessor IGBT3 650V by an optimized vertical structure and proper plasma shaping. This plasma distribution not only determines the performance tradeoff between on-state and switching losses, but at the same time defines the surge voltage for a given Lstray*I in the application as visualized in a switch-off loss vs. surge voltage trade-off diagram. Shaping of the feedback capacitance Cgc optimizes the tunability of the switching slopes by means of an external gate resistor for an easier adaption to a wider range of system inductances with low losses.


Archive | 2003

Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor

Wolfgang Roesner; Richard Johannes Luyken; Johannes Kretz


Archive | 2005

High-density NROM-FINFET

Franz Hofmann; Erhard Landgraf; Richard Johannes Luyken; Wolfgang Roesner; Michael Specht


Archive | 2004

Charge-trapping memory cell and method for production

Michael Specht; Wolfgang Roesner; Franz Hofmann


Archive | 2004

Vertical impedance sensor arrangement and method for producing a vertical impedance sensor arrangement

Franz Hofmann; Richard Johannes Luyken; Wolfgang Roesner


Archive | 2005

Integrated circuit array

Andrew Graham; Franz Hofmann; Wolfgang Hönlein; Johannes Kretz; Franz Kreupl; Erhard Landgraf; Richard Johannes Luyken; Wolfgang Roesner; Thomas Schulz; Michael Specht


Archive | 2000

Field effect transistor used in a switching arrangement comprises a gate region between a source region and a drain region

Johannes Kretz; Johannes R Luyken; Wolfgang Roesner


Archive | 1998

Method of producing a memory cell configuration

Wolfgang Krautschneider; Franz Hofmann; Wolfgang Roesner


Archive | 2005

Process for producing a layer arrangement, and layer arrangement for use as a dual gate field-effect transistor

Gürkan Ilicali; Richard Johannes Luyken; Wolfgang Roesner

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