Erhard Landgraf

Planar and vertical double gate concepts

Abstract In this paper, we report a comparative study of different double gate architectures. The main focus is on the fabrication method of two different device concepts developed in our group. The first is a planar version with special SOI wafers or deposited films and the second is a vertical transistor with lithography independent channel length. In addition to a thorough structural analysis we present electrical characteristics of the fabricated devices.

20 nm tri-gate SONOS memory cells with multi-level operation

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.

Multi-level p+ tri-gate SONOS NAND string arrays

Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found

Validation of 30 nm process simulation using 3D TCAD for FinFET devices

This paper targets to show feasibility of a three-dimensional process simulation flow in the context of optimization of the device design and the underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm FinFET devices. The major goal of the simulation work is to implement a complete FinFET process flow into a commercially available 3D process simulation environment. Furthermore, all important three-dimensional geometrical features, such as corner roundings and 3D facets, have been introduced into the simulation set-up. After the successful demonstration of a functional 3D process simulation flow, detailed issues of process simulation methodology are assessed, such as the usage of different dopant diffusion models or the modelling of specific oxidation processes plus assessment of different annealing conditions. Finally, a comparison of the simulation results with electrical measurement data is performed which shows fairly good agreement.

Hot-carrier induced dielectric breakdown (HCIDB) challenges of a new high performance LDMOS generation

A new generation of embedded-power technologies offering high performance LDMOSFETs was introduced and particularly the reliability of the devices were characterized. The combination of a 120nm logic process with LDMOS with thin gate oxide enables high efficiency power converters on small die sizes. The reliability of the new LDMOS transistors had to be optimized very accurately to achieve both reliable products and the new RON benchmark.

Reduction of layout variations with stress-compensated hybrid STI fills: a comprehensive analysis

Based on a detailed I-V analysis, 2D/3D process/device simulation, and inline wafer bow measurements, we have investigated a number of stress-induced layout effects on MOSFET performance caused by hybrid STI fills (HARP/HDP and SOG/HDP). Variations of active area dimensions, STI widths, and gate lengths were studied in 58 nm DRAM technology. Excellent STI-stress-related device performance variability (overall current and Vth variations smaller than 5% / 10 mV) is demonstrated with a proper choice of STI fill materials and adjusted layer thicknesses.

Full 3D Process and Device Simulation for FinFET optimization

Based on a state-of-the-art 3D process and device simulation framework, we present an extensive analysis of the impact of FinFET process parameters on the device characteristics. The results compare well with the available experimental data.

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

The leakage mechanisms in fully depleted (FD) SOI transistors with undoped channel are investigated. These devices - contrary to partially depleted devices - show a strong V/sub DS/ dependence of the leakage currents. Energy balance simulations, including band to band tunneling effects and impact ionization, have been carried out. Contrary to drift diffusion calculations, these simulations can account for the experimental data and show that the two effects can be separated. In order to reduce these leakage effects, the design of the drain has to be optimised.

Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics

Replacing oxide-nitride-oxide (ONO) dielectrics in charge trapping memories such as SONOS (silicon/ONO/silicon) and NROM (nitrided read only memory) by high-k materials potentially offers improved scaling properties of the devices. In particular, a high dielectric constant of at least one of the three layers allows one to reduce the total equivalent oxide thickness (EOT) thus achieving the same programming electric field as in ONO stacks at reduced voltage. In this study, we evaluate the retention time of charge trapping memories using Al/sub 2/O/sub 3/ as a trapping dielectric and as a control gate dielectric. We find sufficiently large shifts of the threshold voltage allowing for retention times of more than ten years for the Al/sub 2/O/sub 3/ charge trapping memories. High-temperature annealed, polycrystalline layers are found to be more useful than amorphous layers annealed at 400-600/spl deg/C due to better retention time, smaller EOT and flat band shifts and a smaller amount of fixed interface charges.

High On Current in Quasi Double Gate Transistors with Undoped Channel Region

A process flow for the fabrication of a double gate FinFET transistor on SOI material is given. First “quasi” double gate devices with a wide fin are presented. The double gate concept allows for the omission of pn-junctions at Source and Drain, which results in high on currents due to reduced scattering compared to MOSFETs with a doped body. This is confirmed by electrical measurements of pand n-channel devices.