Byeong-In Choe

Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test

Data Retention Characteristics of Nitride-Based Charge Trap Memory Devices with High-

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

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The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (Vth) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL Vth and body doping profile for SSL device. According to simulation work, a high Vth of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron–hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation.

Dielectrics and High-Work-Function Metal Gates for Multi-Gigabit Flash Memory

Through the evaluation and analysis of the data retention characteristics, it was found that the CTF memory cell behaviors are quite different from conventional that of the FG type flash memory cell in terms of Arrhenius plot of data retention because Ea of the CTF memory cell has a high dependency on the bake temperature and P/E cycles. A proper acceleration test condition is needed to predict the data retention lifetime of the CTF memory, considering the change of Ea in the low temperature region (<125°C).

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

Silicon/metal-oxide-nitride-oxide-silicon (SONOS/MONO S) devices receive increasing interest recently due to their simpler process, smaller cell size, and better endurance over the floating-gate devices [1]. However, charge retention and erase speed remain as the major challenges for SONOS devices to replace floating-gate devices [1,2]. Recently, it is reported improved erase performance and endurance characteristics can be achieved by replacing SiO2 and poly-Si as high-k dielectric, Al2O3 and high-work function metal, TaN for blocking oxide and gate material, respectively [3]. However, data retention characteristics still need to be improved since memory window is very small after long time retention. In this work, we present an optimized cell structure for both improved data retention and erase speed in SONOS-type flash EEPROM.

New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory

The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.

Data Retention Characteristics of MONOS Devices with High-k Dielectrics and High-work Function Metal-gates for Multi-gigabit Flash Memory

We present the TANOS (Si-Oxide-SiN-Al 2 O 3 -TaN) cell with 40 A-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al 2 O 3 ) as a blocking oxide, the erase threshold voltage can be maintained to less than - 3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.